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Configuration and Installation Chapter 2
PC-TIO-10 User Manual 2-12 © National Instruments Corporation
Am9513A Digital Output Specifications (referenced to GND):
Minimum Maximum
Output logic high voltage, all outputs
at Iout = -200
µ
A 2.4 V 5.0 V
Output logic low voltage, all outputs
at Iout = 3.2 mA 0.0 V 0.4 V
Figure 2-9 shows the timing requirements for the GATE and SOURCE input signals and the
timing specifications for the OUT signals of the Am9513A STCs.
t
sc
145 nsec Minimum
t
sp
70 nsec Minimum
t
gsu
100 nsec Minimum
t
gh
10 nsec Minimum
t
gw
145 nsec Minimum
t
out
300 nsec Maximum
t
sc
t
sp
t
sp
SOURCE
V
I H
V
I L
t
out
OUT
V
I H
V
I L
t
gw
t
gsu
t
gh
GATE
V
I H
V
I L
Figure 2-9. Timing Signal Relationships
The GATE and OUT signal transitions in Figure 2-9 are referenced to the rising edge of the
SOURCE signal. This timing diagram assumes that the counters are programmed to count rising
edges. The same timing diagram, with the source signal inverted and referenced to the falling
edge of the source signal, applies to the case in which the counter is programmed to count falling
edges.
The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A
counter/timers and by the Am9513A frequency division output FOUT. The signal applied to a
SOURCE input must not exceed a frequency of 7 MHz for proper operation of the Am9513A.
The Am9513A counters can be individually programmed to count rising or falling edges of
signals applied at any of the Am9513A SOURCE or GATE input pins.
In addition to the signals applied to the SOURCE and GATE inputs, the Am9513A generates
five internal timebase clocks from the clock signal supplied by the PC-TIO-10. The five internal