RMC SD via FPGA DIO Throughput
Read
8.0 MB/s maximum
Write
6.5 MB/s maximum
Note
RMC SD has slower throughputs as the Xilinx Zynq-7000 requires SD
interfaces through the FPGA to operate at standard speed rather than at high speed.
3.3 V Digital I/O on RMC Connector
Number of DIO channels
96
Maximum tested current per channel
±3 mA
Note
The performance of the RMC DIO pins is bounded by the FPGA, signal
integrity, the application timing requirements, and the RMC design. A general SPI
application will typically be able to meet these requirements and achieve frequencies
of up to 10 MHz. For more information on using DIO to connect to RMCs, visit
ni.com/info
and enter the Info Code
RMCDIO
.
Input logic levels
Input low voltage, V
IL
-0.3 V minimum; 0.8 V maximum
Input high voltage, V
IH
2.0 V minimum; 3.45 V maximum
Output logic levels
Output high voltage, V
OH
when sourcing 3 mA
2.4 V minimum; 3.45 V maximum
Output low voltage, V
OL
when sinking 3 mA
0.0 V minimum; 0.4 V maximum
3.3 V Digital I/O on 50-Pin IDC Connector
Number of DIO channels
4
Maximum tested current per channel
±3 mA
Input logic levels
Input low voltage, V
IL
-0.3 V minimum; 0.8 V maximum
Input high voltage, V
IH
2.0 V minimum; 5.25 V maximum
NI sbRIO-9627 Specifications
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© National Instruments
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