Chapter 2
NI 5450 Overview
©
National Instruments Corporation
2-37
NI PXIe-5450 User Manual
Internal Sample Clock
The NI 5450 can derive a Sample clock from its main internal timing
source—the Sample clock timebase. The signal generator provides a
high-precision 400 MHz oscillator clock source for the Sample clock
timebase.
The following figure shows the NI 5450 internal Sample clock Source path.
The NI 5450 has a high-resolution internal clock. You can change the
frequency of this clock by calling the niFgen Set Sample Rate VI or the
niFgen_ConfigureSampleRate
function. When you set a desired
sample rate, NI-FGEN will internally determine and apply appropriate
divide-down factors.
Note
The jitter of the High-Resolution clocking mode is frequency–dependent. At low
frequencies the jitter increases. Refer to the device specifications for more information
about jitter.
Phase-Locked Loop Reference Clock
A phase-locked loop (PLL) is a circuit that tunes the Sample clock timebase
to phase–lock to an external Reference clock. The PLL Reference clock
source controls the source of the control voltage that tunes the VCXO of
the Sample clock timebase for internal clock update sources. The frequency
stability and accuracy of the Sample clock timebase matches that of the
Reference clock when they are phase–locked. Using the PLL on your
device enables you to frequency-lock multiple devices in a single chassis
or devices in separate chassis.
Note
Refer to the device specifications for information about the PLL reference
frequencies available on your device.
PXI_CLK10
CLK IN
High
Resolution
Oscillator
PLL
CLK OUT
(None)
Divide/M
Sample Clock
Timebase/M
PLL* W
with Phase
Adjust
Divide/N
Sample
Clock
Timebase
Channel
Delay
Channel
Delay
CH 0
Sample Clock
CH 1
Sample Clock
Divide/K
Reference Clock
External Sample Clock
External Sample Clock Timebase
