©
National Instruments
19
8-Slot NI PXIe-1082 Backplane Installation Guide
Output amplitude.................................... 1 V
PP
±20% square-wave
into 50
Ω
2 V
PP
unloaded
Output impedance .................................. 50
Ω
± 5
Ω
External Clock Source
Frequency............................................... 10 MHz ±100 PPM
Input amplitude
J36 ................................................... 200 mV
PP
to 5 V
PP
square-wave
or sine-wave
System timing slot
PXI_CLK10_IN.............................. 5 V or 3.3 V TTL signal
J36 input impedance............................... 50
Ω
± 5
Ω
Maximum jitter introduced
by backplane .......................................... 1 ps RMS phase-jitter (10 Hz to
1 MHz range)
PXIe_SYNC_CTRL
V
IH
.......................................................... 2.0 to 5.5 V
V
IL
.......................................................... 0 to 0.8 V
PXI Star Trigger
Maximum slot-to-slot skew ................... 250 ps
Backplane characteristic impedance ...... 65
Ω
±10%
Note
For PXI slot to PXI Star mapping, refer to the
System Timing Slot
section of
Chapter 1,
Getting Started
, in the
NI PXIe-1082 User Manual
.
Note
For other specifications, refer to the
PXI-1 Hardware Specification
.
PXI Differential Star Triggers (PXIe-DSTARA,
PXIe-DSTARB, PXIe-DSTARC)
Maximum slot-to-slot skew ................... 150 ps
Maximum differential skew ................... 25 ps
Backplane differential impedance.......... 100
Ω
±10%