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National Instruments Corporation
7
8-Slot NI PXIe-1062Q Backplane Installation Guide
An independent buffer drives PXIe_SYNC100 to the hybrid peripheral slot
and system timing slot. Refer to Figure 4 for the routing configuration of
PXIe_SYNC100. These clocks are matched in skew to less than 100 ps.
The differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_SYNC100, so that when there is
no peripheral or a peripheral that does not connect to PXIe_SYNC100, no
SYNC100 signal is driven on the pair to that slot.
Figure 4.
Distribution of PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100
PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 have the default timing
relationship described in Figure 5.
Figure 5.
System Reference Clock Default Behavior
PXI_CLK10
PXI_CLK10_IN
PXIe_CLK100
PXIe_SYNC100
System Controller Slot (1)
PXI P
e
ripher
al Slot (2)
Hybr
id P
e
ripher
al Slot (3)
System
Timing Slot (4)
Hybr
id P
e
ripher
al Slot (5)
PXI P
e
ripher
al Slot (6)
PXI P
e
ripher
al Slot (7)
PXI P
e
ripher
al Slot (8)
10 MHz
REF IN
10 MHz
REF OUT
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
