NI 5731/5732/5733/5734R User Guide and Specifications
14
ni.com
14. Wire an indicator to the output terminal of the
IO Module\AI 0 Data N node.
15. Add the Close FPGA VI Reference function, located on the
FPGA Interface
palette, to the right
of the While Loop on the block diagram.
16. Wire the
FPGA VI Reference Out
terminal of the Read/Write Control
function to the
FPGA VI
Reference In
terminal of the Close FPGA VI Reference
function.
17. Wire the
error out
terminal of the Read/Write Control function
to the
error in
terminal of the
Close FPGA VI Reference function.
Your block diagram should now resemble the block diagram in Figure 7.
Figure 7.
573xSampleAcq(Host).vi Block Diagram
18. Save the VI as
573xSampleAcq(Host).vi
.
Running the Host VI
1.
Connect one end of an BNC cable to AI 0 on the front panel of the NI 5731/5732/5733/5734 and
the other end of the cable to your DUT.
2.
Open the front panel of
573xSampleAcq(Host).vi
.
3.
Click the
Run
button to run the VI.
4.
The VI acquires data from the DUT on AI 0 Data N.
5.
Click the
STOP
button on the front panel and close the VI.
Note
(NI 5731 Only)
ESD events can affect the NI 5731 Sample clock, which can cause error
-50400
when performing DMA transfers or result in other clock performance and timeout errors
when acquiring data on the NI 5731. To ensure that the NI 5731 self-recovers from this error, the host
and FPGA VIs must be able to trap these timeout errors and reinitialize the FPGA. The following two
steps describe how to self-recover the NI 5731:
1.
For more information about how to trap the error, visit the KnowledgeBase at
ni.com/kb
, enter
3BPD5HRY
, and select the article,
Ignoring a Particular Error in an Error Cluster in LabVIEW
.
2.
To reinitialize the FPGA, refer to the
Reset (Invoke Method)
topic in the
NI FPGA Module Help
file, available in LabVIEW and at
ni.com/manuals
.
Содержание NI 5731
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