National Instruments NI 5401, Руководство пользователя

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Chapter 2 Function Generator Operation
© National Instruments Corporation 2-11 NI 5401 User Manual
Phase-Locked Loops and Board Synchronization
Figure 2-11 illustrates the block diagram for the NI 5401 for PCI PLL
circuit. Figure 2-12 illustrates the block diagram for the NI 5401 for PXI
PLL circuit. The PLL consists of a voltage-controlled crystal oscillator
(VCXO) with a tuning range of ±100 ppm. This VCXO generates the main
clock of 80 MHz.
The PLL can lock to a reference clock source from the external connector,
from an RTSI Osc line on the RTSI bus (NI 5401 for PCI), or from a
10 MHz Osc line on the PXI backplane bus (for NI 5401 for PXI). The PLL
can also be tuned internally using a calibration DAC (CalDAC). National
Instruments accurately performs this tuning during manufacturing. Refer to
the
RTSI/PXI Trigger Lines section later in this manual for additional
information on using the RTSI and 10 MHz Osc lines.
The reference and VCXO clock are compared by a phase comparator
running at 1 MHz. The loop filters the error signal and sends it to the control
pin of the VCXO to complete the loop.
Figure 2-11. PLL Architecture for the NI 5401 for PCI
80 MHz
Div/4
VCXO
Board Clock (Master)
RTSI Clock (Slave)
Master/Slave
RTSI
Switch
RTSI
Bus
RTSI Osc
Board Clock
20 MHz
Loop
Filter
Tune
DAC
PLL Ref
(1 V
pk-pk
min)
Control
Voltage
(20 MHz)
Source
14
Phase
Comp
AMUX