Chapter 9
Digital Routing and Clock Generation
©
National Instruments Corporation
9-9
An S Series device receives the Star Trigger signal (PXI_STAR) from a
Star Trigger controller. PXI_STAR can be used as an external source for
many AI, AO, and counter signals.
An S Series device is not a Star Trigger controller. An S Series device may
be used in the first peripheral slot of a PXI system, but the system will not
be able to use the Star Trigger feature.
PXI_STAR Filters
(NI 6124 Only)
You can enable a programmable debouncing filter on each
PFI, RTSI, or PXI_STAR signal. When the filters are enabled, your device
samples the input on each rising edge of a filter clock. S Series devices use
an onboard oscillator to generate the filter clock with a 40 MHz frequency.
Note
NI-DAQmx
only
supports filters on counter inputs.
The following is an example of low to high transitions of the input signal.
High to low transitions work similarly.
Assume that an input terminal has been low for a long time. The input
terminal then changes from low to high, but glitches several times. When
the filter clock has sampled the signal high on N consecutive edges, the low
to high transition is propagated to the rest of the circuit. The value of N
depends on the filter setting; refer to Table 9-3.
Table 9-3.
Filters
Filter Setting
N (Filter Clocks
Needed to
Pass Signal)
Pulse Width
Guaranteed to
Pass Filter
Pulse Width
Guaranteed to
Not Pass Filter
125 ns
5
125 ns
100 ns
6.425
μ
s
257
6.425
μ
s
6.400
μ
s
2.56 ms
~101,800
2.56 ms
2.54 ms
Disabled
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