Figure 7.
PFI <1..3> Port
PFI from
NI FlexRIO
FPGA Module
3
PFI Output Enable
from NI FlexRIO
FPGA Module
PFI to
NI FlexRIO
FPGA Module
3
3
DDC
Voltage Reference
Internal/External
Note
Digital I/O signals, P0 <0..7>, P1 <0..7>, P2 <0..7>, and PFI <1..3>, appear
on both connectors, DDCA and DDCB.
Figure 8.
Clock Input and Output
Global Clock
to NI FlexRIO
FPGA Module
Clock from
NI FlexRIO
FPGA Module
DDC
Clock Out
DDC Global
Clock In
Voltage Reference
Internal/External
Output Enable
from NI FlexRIO
FPGA Module
Note
Refer to Tables 3 and 4 for information about buffer mapping to the NI
FlexRIO FPGA module.
NI 6581/6581B Component-Level Intellectual
Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration of the user-defined CLIP, but also allows
the CLIP to communicate directly with circuitry external to the FPGA. Adapter module
socketed CLIP allows your IP to communicate directly with both the FPGA VI and the
external adapter module connector interface.
The following figure shows the relationship between an FPGA VI and the CLIP.
NI 6581/6581B Getting Started Guide
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© National Instruments
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