Chapter 2
Register Map and Descriptions
©
National Instruments Corporation
2-13
6527 Register-Level Programmer Manual
Falling-Edge Detection Registers (Ports 0–2)
These registers enable edge detection interrupts for falling edges on selected lines of input
ports. To generate interrupts you must also set the EdgeInt bit in the Master Interrupt Control
Register.
Address Offsets:
20 (hex) for Port 0
21 (hex) for Port 1
22 (hex) for Port 2
Type:
Read and write
Size:
8-bit
Bit Map:
Bit
Name
Description
7–1
Fall.<7..0>
Falling-Edge Detection enables—Each bit enables
interrupt generation on falling edges of the corresponding
input line.
1 = Falling-edge detection enabled
0 = Falling-edge detection disabled
7
6
5
4
3
2
1
0
Fall.7
Fall.6
Fall.5
Fall.4
Fall.3
Fall.2
Fall.1
Fall.0
