Chapter 4
Signal Connections
4-28
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As an input, the CONVERT* signal is configured in the edge-detection
mode. You can select any PFI pin as the source for CONVERT* and
configure the polarity selection for either rising or falling edge. The
selected edge of the CONVERT* signal initiates an A/D conversion.
The ADC switches to hold mode within 60 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary from
one conversion to the next. CONVERT* pulses should be separated by at
least 5
µ
s (200 kHz sample rate)
As an output, the CONVERT* signal reflects the actual convert pulse that
is connected to the ADC. This is true even if the conversions are being
externally generated by another PFI. The output is an active low pulse with
a pulse width of 50 to 150 ns. This output is set to tri-state at startup.
Figures 4-21 and 4-22 show the input and output timing requirements for
the CONVERT* signal.
Figure 4-21.
CONVERT* Input Signal Timing
Figure 4-22.
CONVERT* Output Signal Timing
The sample interval counter on the device normally generates the
CONVERT* signal unless you select some external source. The counter is
started by the STARTSCAN signal and continues to count down and reload
itself until the scan is finished. It then reloads itself in preparation for the
next STARTSCAN pulse.
Rising-Edge
Polarity
Falling-Edge
Polarity
t
w
t
w
= 10 ns minimum
t
w
t
w
= 50-150 ns