NI 5762R User Guide and Specifications
6
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Block Diagram
Figure 3 shows a block diagram image of the signal flow to and from the NI 5762 adapter module and
the NI 5762 component-level intellectual property (CLIP) in LabVIEW FPGA.
Figure 3.
NI 5762 Connector Signals and NI 5762 CLIP Signal Block Diagram
NI 5762 Adapter Module
AI 0
AI 1
TRIG
CLK IN
DIO Port 0 (0)
DIO Port 0 (1)
DIO Port 0 (2)
DIO Port 0 (3)
DIO Port 1 (0)
DIO Port 1 (1)
DIO Port 1 (2)
DIO Port 1 (3)
PFI 0
PFI 1
PFI 2
PFI 3
A
UX I/O
AD9647
Analog
In
Path
ADC Clock
ADC Data
ADC Control
Clk Function
PLL Locked
Enable VCX0
SClk
I2C (Shared)
Sda
Clk Control
Sample Clock
AD9647
AD9511
LabVIEW FPGA CLIP
Analog
In
Path
PLL Loop
Filter
ADT7408
Temperature
Sensor
User
EEPROM
250 MHz
VCXO
Enable PLL
ADC Clock
ADC Data
ADC
Interface
ADC
Interface
AI 0 Data (N and N-1)
AI 1 Data (N and N-1)
Trigger Input
Sync Clock (IoModSyncClk)
PLL Locked
Initialization Done
Reinitialize
AI 0 Data Over Range
AI 1 Data Over Range
16
16
Configuration Error
Configuration Error Code
SPI Device Select
SPI Read
SPI Write
SPI Write Data
SPI Address
SPI Read Data
SPI Idle
SPI Engine
16
16
DIO Port 0 WE
DIO Port 0 Rd Data (0)
DIO Port 0 Wr Data (0)
DIO Port 0 Rd Data (1)
DIO Port 0 Wr Data (1)
DIO Port 0 Rd Data (2)
DIO Port 0 Wr Data (2)
DIO Port 0 Rd Data (3)
DIO Port 0 Wr Data (3)
DIO Port 1 Rd Data (0)
DIO Port 1 Wr Data (0)
DIO Port 1 Rd Data (1)
DIO Port 1 Wr Data (1)
DIO Port 1 Rd Data (2)
DIO Port 1 Wr Data (2)
DIO Port 1 Rd Data (3)
DIO Port 1 Wr Data (3)
DIO Port 1 WE
PFI 3 Wr Data
PFI <0..3> WE
PFI 3 Rd Data
PFI 1 Rd Data
PFI 1 Wr Data
PFI 2 Rd Data
PFI 2 Wr Data
PFI 0 Rd Data
PFI 0 Wr Data
4
Sample Clock Select
Sample Clock Commit
User EEPROM Write Data Successful
User EEPROM Address
User EEPROM Read
User EEPROM Write
User EEPROM Read Data
Measure Temperature
I2C Timeout
Temperature
Temperature Valid
User EEPROM Read Data Valid
User EEPROM Write Data
