NAD C715, Руководство по обслуживанию

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Signal Name Shared Signal Pin # Type Description – TCC760
GPIO_A[0] SDO0 / FGPIO[0] 104 I/O
GPIO_A[0] / General purpose serial I/O 0 Serial Data Output
FGPIO[0]
GPIO_B[29:28] USBH_DN, USBH_DP 54:53 I/O GPIO_B[29:28] / USBH_DN, USBH_DP
GPIO_B[27:26] USB_DN, USB_DP 52:51 I/O GPIO_B[27:26] / USB_DN, USB_DP
GPIO_B[25]
GPIO_B[24] / BM[2]
GPIO_B[23]
GPIO_B[22] / BM[1]
GPIO_B[21] / BM[0]
DAI
DAO
MCLK
LRCK
BCLK
68
67
66
63
62
I/O
GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
GPIO_B[9] UT_RX 61 I/O GPIO_B[9 ] / UART RX Signal
GPIO_B[8] UT_TX / SD_nCS 60 I/O GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select
GPIO_B[7] ND_nWE 57 I/O GPIO_B[7] / Write Enable for NAND Flash
GPIO_B[5:2] nCS[3:0] 50:47 I/O GPIO_B[5:2] / External Chip Select 3 ~ 0
GPIO_B[1] SD_nCS / SD_nCLK 46 I/O
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
SDRAM.
GPIO_B[0] SD_CKE 56 I/O GPIO_B[0] / SDRAM clock control
GPIO_D[21:18] FGPIO[13:10] / CISD[7:4] 96:93 I/O
GPIO_D[21:18] / Fast GPIO bits 13 ~10 / Camera Interface Data
Inputs 3 ~ 0. Internal pull-up resistors are enabled at reset.
GPIO_D[17] FGPIO[9] / SCL / CISHS 92 I/O GPIO_D[17] / Fast GPIO bit 9 / I2C SCL / Camera Interface Hsync.
GPIO_D[16] FGPIO[8] / SDA / CISVS 91 I/O GPIO_D[16] / Fast GPIO bit 8 / I2C SDA / Camera Interface Vsync.
GPIO_D[15] CISCLK 90 I/O GPIO_D[15] / Camera Interface Clock
ADC Input Pins
ADIN_0 - 82 AI General purpose multi-channel ADC input 0
ADIN_2 - 83 AI General purpose multi-channel ADC input 2
ADIN_4 - 84 AI General purpose multi-channel ADC input 4
Clock Pins
XIN - 74 I Main Crystal Oscillator Input for PLL. 12MHz Crystal
must be used if USB Boot Mode is required. Input
voltage must not exceed VDD_OSC (1.95V max).
XOUT - 75 O Main Crystal Oscillator Output for PLL
XFILT - 78 AO PLL filter output
XTIN - 69 I Sub Crystal Oscillator Input. 32.768kHz is recommended.
Input voltage must not exceed VDD_OSC (1.95V max).
XTOUT - 70 O Sub Crystal Oscillator Output
Mode Control Pins
MODE1 - 98 I Mode Setting Input 1. Pull-down for normal operation.
PKG1 - 89 I Package ID1, Pull-up for normal operation.
nRESET - 72 I System Reset. Active low.
JTAG Interface Pins
TDI - 99 I JTAG serial data input for ARM940T
TMS - 100 I JTAG test mode select for ARM940T
TCK - 101 I JTAG test clock for ARM940T
TDO - 102 I/O JTAG serial data output for ARM940T. External pull-up resistor is
required to prevent floating during normal operation.
nTRST - 103 I JTAG reset signal for ARM940T. Active low.
Power Pins
VDDIO - 112
76
33
16
PWR Digital Power for I/O (1.8V ~ 3.3V)
2
- 30