NAMC-ZYNQ-FMC – Board Support Package Manual
Version 1.0
© N.A.T. GmbH
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makefile delivered with the bsp. The /vivado folder contains the hardware reference
project that can be used as a template for bitstream generation. The overview of the
folder structure is shown at the table below:
bsp
Petalinux project folder (bsp=project name)
>
build
Object files from build process
>
components
Contains FSBL sources
>
hw-description
Contains FPGA configuration file
>
images
Contains images for booting the device
>
subsystems
Several configuration files (device tree, startup configs)
doc
Documentation
src
User defined sources
>
patches
Patch files
>
components
Linux-Kernel and U-boot sources
>
apps
User applications
vivado
Vivado project folder containing reference
hardware design for NAMC-ZYNQ-FMC
Table 1: BSP folder structure
1.4
Vivado reference design
The BSP has a folder /vivado witch contains the reference design for the ZYNQ FPGA that
customers may use as a template for developing further logic on top of that. The design
was created with Vivado 2015.2.1. Opening and compiling the design requires a license
file for the ZYNQ FPGA device (xc7z045ffg900-2) that can be purchased at Xilinx store.
The design brings a block diagram (see figure below) with basic communication and
memory interfaces, such as Ethernet, AXI PCIe and a DDR3 memory controller. There is
also an instance that serves 100 MHz telecom clocks TCLKB, TCLKD to the backplane. To
use that feature, just change the constant value from “0” to “1”.
For interfacing with the FMC using SPI or I2C protocol you may use the FPGA EMIO to
route these protocols directly into the ARM core. That will enable you to use the
peripherals quickly within the standard linux drivers. All you need to do is to assign the
FMC I/O pin to the IIC_1 and SPI_0 interface before implementing the design.