Multitech MultiConnect xDot MTXDOT Series, Руководство разработчика

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SPECIFICATIONS AND PIN INFORMATION
MultiConnect
®
xDot
TM
MTXDOT Developer Guide 25
Sleep Wake and Deep Sleep Wake Pins
Pin Description
Sleep Wake
PA9 UART1_RX
PA4 GPIO0
PA5 GPIO1
PB0 GPIO2
PB2 GPIO3
PA0 Wake
Deep Sleep Wake
PA0 Wake
InterruptIn Limitations
Due to the processor's architecture, only one pin of the same number (e.g. PA_1 & PB_1) may be configured as an
InterruptIn. If you configure multiple pins of the same number as InterruptIn, only the last pin configured will
actually trigger an interrupt in the processor. The rest will be ignored.
Note: Pin numbers 1, 6, 7, 8, and 13 are used internally as interrupts from the LoRa radio and may not be
configured as external interrupts. Doing so breaks the xDot's LoRa functionality and causes undefined behavior.
For example, if you configure the WAKE (PA_0) pin to wake the xDot from low power modes and then configure
GPIO2 (PB_0) as an InterruptIn, the WAKE pin will not wake the xDot.