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ROM PCI / ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC
AUTO Configuration :Enabled
CPU to PCI Burst Mem. WR :Disable
ISA Bus Clock Frequency :PCICLK/4
L2 (WB) Tag Bit Length :8bits
System BIOS Cacheable :Enabled
SRAM Back-to-Back :Enabled
Video BIOS Cacheable :Enabled
Starting Point of Paging :1T
Memory Hole at 15M-16M :Disabled
Refresh Cycle Time (us) :15.6
Linear Mode SRAM Support :Disabled
RAS Pulse Width Refresh :6T
RAS Precharge Time :4T
RAS to CAS Delay :4T
CAS# Pulse Width (FP) :2T
CAS# Pulse Width (EDO) :1T
CAS Precharge Time (FP) :1T/2T
CAS Precharge Time (EDO) :1T/2T
SDRAM WR Retire Rate :X-2-2-2
ESC : Quit
↑↓→←
: Select Item
SDRAM Wait State Control :1WS
F1 : Help PU/PD/+/- : Modify
Read Prefetch Memory RD :Enabled
F5 : Old Values (Shift) F2 : Color
CPU to PCI Post Write :4T
F7 : Load Setup Defaults
Chipset Features Setup Screen
※
All of the above entries on the screen are standard settings for this
mainboard and should not be changed unless you are absolutely sure of
what you are doing.
B. ISA Bus Clock Frequency
The PCI clock speed is the CPU bus speed divided in half. The ISA bus speed
is derived from the PCI clock speed and has a maximum bandwidth of 8MHz.
Select the value that results in the closest number to 8 when dividing the PCI
clock by 3 or 4. If you are using a frequency higher than 66 MHz bus speed use
the 7.159MHz option.
C. System/Video BIOS Cacheable
This function allows BIOS values to be temporarily placed into the system's
cache memory. System performance slightly increases when these functions
are enabled.
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Содержание R547
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