MSI Z68A-G45 B3 Series, Руководство пользователя

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MS-7750 Mainboard
English
En-27
MS-7750 Mainboard
English
EIST
The Enhanced Intel SpeedStep technology allows you to set the performance level of
the microprocessor whether the computer is running on battery or AC power. This field
will appear after you installed the CPU which supports speedstep technology.
Intel Turbo Boost
This item will appear when you install a CPU with Intel Turbo Boost technology. This
item is used to enable/ disable Intel Turbo Boost technology. It can scale processor
frequency higher dynamically when applications demand more performance and TDP
headroom exists. It also can deliver seamless power scalability (Dynamically scale up,
Speed-Step Down). It is the Intel newly technology within newly CPU.
OC Genie Button Operation
This field is used to enable/ disable OC Genie function.
DRAM Frequency
This item allows you to adjust the DRAM frequency. Please note the overclocking
behavior is not guaranteed.
Adjusted DRAM Frequency
It shows the adjusted DRAM frequency. Read-only.
DRAM Timing Mode
Select whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [Auto] enables DRAM timings and the
following “Advanced DRAM Configuration” sub-menu to be determined by BIOS based
on the configurations on the SPD. Selecting [Link] or [Unlink] allows users to configure
the DRAM timings and the following related “Advanced DRAM Configuration” sub-menu
manually.
Advanced DRAM Configuration
Press <Enter> to enter the sub-menu.
Command Rate
This setting controls the DRAM command rate.
tCL
This controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it.
tRCD
When DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
tRP
This setting controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumulate its
charge before DRAM refresh, refreshing may be incomplete and DRAM may fail
to retain data. This item applies only when synchronous DRAM is installed in the
system.
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