Chapter 3
3-14
Note:
Change these settings only if you are familiar with the chipset
Item Help
Menu Level
8
Configure DRAM Timing
[by SPD]
CAS# Latency
[3]
Prechare Delay
[7]
RAS# to CAS# Delay
[3]
RAS# Precharge
[3]
DRAM Data Integrity Mode
[Non-ECC]
DRAM Frequency
[Auto]
Memory Hole At 15M-16M
[Disabled]
Delayed Transaction
[Enabled]
AGP Aperture Size (MB)
[64]
CMOS Setup Utility - Copyright(C) 1984-2001 Award Software
Advanced Chipset Features
↑ ↓ → ←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-safe Defaults F7:Optimized Defaults
Advanced Chipset Features
Configure DRAM Timing
This allows you to select whether DRAM timing is controlled by the SPD
(Serial Presence Detect) EPROM on the DRAM module or by the user.
When set to [by SPD] as default, the following four items are automatically
determined by BIOS based on the configurations on the SPD. When set
to [by User], you can configure these items manually. Available options
are [by SPD]
and [
by User].
CAS# Latency
This item controls the timing delay (in clock cycles) before SDRAM starts
a read command after receiving it. Available options are [2] and [3]; the
value should be set depending on the SDRAM installed.
Precharge Delay
This item controls the number of clock cycles for DRAM to be allowed to
precharge from the active state.
Available options are [
7], [6], and [5].
