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CHAPTER 3
AMI
®
BIOS USER’S GUIDE
3-10
Primary Frame Buffer
The processor provides a write-combining with buffering strategy for
write operation. This is useful for frame buffering. Writing to USWC
memory can be buffered and combined in the processor’s write-combining
buffer (WCB). The WCBs are viewed as a special purpose outgoing write
buffers, rather than a cache. The WCBs are written into memory to allocate a
different address, or after executing a serializing, locked, or I/O instructions.
During Enabled, this will enable the processor memory location C000
and DFFF segment as USWC memory type.
VGA Frame Buffer
The processor provides a write-combining with buffering strategy
for write operation. This is useful for frame buffering. Writing to USWC
memory can be buffered and combined in the processors write-combining
buffer (WCB). The WCBs are viewed as a special purpose outgoing write
buffers, rather than a cache. The WCBs are written into memory to allocate a
different address. or after executing a serializing, locked, or I/O instructions.
During Enabled, this will enable the processor memory location
A000 and B000 segment as USWC memory type.
Data Merge
During Enabled, this will use the Burst Cycle for Data Transfer.
The default setting is Disabled.
Passive Release
During Enabled, this will allow the chipset to use passive release
while transferring control information or data for transaction. During
Disabled, chipset will perform PCI accesses without using passive release.
ISA Line Buffer
When an ISA/DMA master reads from the PCI memory, the M1543
chipset prefetches 8 bytes of data into the line buffer. Default setting is
Enabled.