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Glossary
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POWER
Performance Optimized With Enhanced RISC architecture (IBM)
PowerPC™
The trademark used to describe the Performance Optimized With
Enhanced RISC microprocessor architecture for Personal
Computers developed by the IBM Corporation. PowerPC is
superscalar, which means it can handle more than one instruction
per clock cycle. Instructions can be sent simultaneously to three
types of independent execution units (branch units, fixed-point
units, and floating-point units), where they can execute
concurrently, but finish out of order. PowerPC is used by
Motorola, Inc. under license from IBM.
PowerPC 601™
The first implementation of the PowerPC family of
microprocessors. This CPU incorporates a memory management
unit with a 256-entry buffer and a 32KB unified (instruction and
data) cache. It provides a 64-bit data bus and a separate 32-bit
address bus. PowerPC 601 is used by Motorola, Inc. under license
from IBM.
PowerPC 603™
The second implementation of the PowerPC family of
microprocessors. This CPU incorporates a memory management
unit with a 64-entry buffer and an 8KB (instruction and data)
cache. It provides a selectable 32-bit or 64-bit data bus and a
separate 32-bit address bus. PowerPC 603 is used by Motorola,
Inc. under license from IBM.
PowerPC 603e™
A variant of the second implementation of the PowerPC family of
microprocessors. This CPU incorporates a faster clock (100MHz)
and 256KB L2 cache. PowerPC 603e is used by Motorola, Inc.
under license from IBM.
PowerPC 604™
The third implementation of the PowerPC family of
microprocessors. PowerPC 604 is used by Motorola, Inc. under
license from IBM.
PowerPC Reference Platform (PRP)
A specification published by the IBM Power Personal Systems
Division which defines the devices, interfaces, and data formats
that make up a PRP-compliant system using a PowerPC processor.
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