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Functional Description
3
Two-Wire Serial Interface
A two-wire serial interface for the MVME2100 is provided by an I
2
C
compatible serial controller integrated into the processor’s peripheral
device. The processor’s serial controller is used by the system software to
read the contents of the configuration EEPROM contained on the board.
I
2
O Message Unit
I
2
O compliant messaging for the MVME2100 is provided by an I
2
O
compliant messaging unit integrated into the processor’s peripheral
device. The processor’s message unit can operate with either generic
messages and door bell registers, or as an I
2
O compliant interface.
Direct Memory Access (DMA)
The MVME2100 provides DMA capability through a two-channel DMA
controller integrated into the processor’s peripheral device. Each DMA
channel is capable of performing local memory to local memory, PCI
memory to local memory, local memory to PCI memory and PCI memory
to PCI memory data transfers.
Both DMA channels can be accessed by the local CPU as well as external PCI
bus masters and support unaligned transfers, data chaining, and scatter gather.
Timers
Timing functions for the MVME2100 are provided by four independent
31-bit timers integrated into the processor. The four timers are clocked at
1/8 of the processor clock rate. Each timer contains four registers enabling
the system software to set the count values, enable or disable the timer,
enable or disable interrupt generation, set the interrupt priority level, and
to generate an interrupt vector.
