2-16
Board Level Hardware Description
2
Motorola software
does
support mixed parity and ECC memory
boards on the same main board.
The DRAM is four-way interleaved to efficiently support cache
burst cycles.
Onboard DRAM mezzanines are available in these configurations:
❏
4, 8, 16, or 32MB with parity protection
❏
4, 8, 16, 32, 64, or 128MB with ECC protection
Stacking Mezzanines
Two mezzanine boards may be stacked to provide up to 256MB of
onboard RAM (ECC).
❏
The main board and a single mezzanine board together take
one slot.
❏
The stacked configuration requires two VMEboard slots.
DRAM Programming Considerations
❏
The DRAM map decoder can be programmed to
accommodate different base address(es) and sizes of
mezzanine boards.
❏
The onboard DRAM is disabled by a local bus reset and must
be programmed before the DRAM can be accessed.
❏
Most DRAM devices require some number of access cycles
before the DRAMs are fully operational.
Ð Normally this requirement is met by the onboard refresh
circuitry and normal DRAM installation. However,
software should insure a minimum of 10 initialization
cycles are performed to each bank of RAM.
Refer to the MEMC040 or the MCECC in the
Single Board Computers
Programmer's Reference Guide
for detailed programming
information.
Содержание MVME167 Series
Страница 1: ...MVME167 Single Board Computer Installation Guide MVME167IG D4 ...
Страница 6: ......
Страница 106: ...4 28 Debugger General Information 4 ...
Страница 132: ...5 26 Using the 167Bug Debugger 5 ...
Страница 146: ...A 14 Configure and Environment Commands A ...
Страница 152: ...B 6 Disk Tape Controller Data B ...
Страница 160: ...D 6 Troubleshooting the MVME167 Solving Startup Problems D ...
Страница 168: ...E 8 EIA 232 D Interconnections E ...