Motorola MC68HC05T16, Технические данные инструкция

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MOTOROLA
5-4 MC68HC05T16 TIMERS
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bits are readable and writable and are not affected by the timer hardware or reset. If the compare
function is not needed, the Output Compare registers can be used as storage locations.
The contents of the Output Compare registers are continually compared with the contents of the
free-running counter and, if a match is found, the corresponding output compare flag (OC0F or
OC1F) in the Timer Status register is set. The Output Compare registers’ value should be changed
after each successful comparison to establish a new elapsed time-out. An interrupt can also
accompany a successful output compare provided the corresponding interrupt enable bit (OC0IE
or OC1IE) is set. (The free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the Output Compare registers containing the MSB ($14 or $16),
the output compare function is inhibited until the LSB ($15 or $17) is also written. The user must
write both bytes (locations) if the MSB is written first. A write made only to the LSB ($15 or $17)
will not inhibit the compare function. The processor can write to either byte of an Output Compare
register without affecting the other byte. The minimum time required to update the Output
Compare registers is a function of the program rather than the internal hardware. Because the
output compare flags and Output Compare registers are not defined at power on, and not affected
by reset, care must be taken when initializing output compare functions with software. The
following procedure is recommended:
1) write to Output Compare register 0 and/or 1 High-byte to inhibit further
compares;
2) read the Timer Status register to initialize clearing of OC0F or/and OC1F;
3) write to Output Compare register 0 or/and 1 Low-byte to enable the output
compare function.
5.1.3 Input Capture Registers
– Input Capture Register High byte - $12, Low byte - $13
‘Input Capture’ is a technique whereby an external signal (connected to TCAP pin) is used to
trigger a read of the free-running counter. In this way it is possible to relate the timing of an external
signal to the internal counter value, and hence to elapsed time.
The two 8-bit registers that make up the 16-bit input capture register, are read-only, and are used
to latch the value of the free-running counter after the corresponding input capture edge detector
senses a valid transition. The level transition that triggers the counter transfer is defined by the
corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture
register.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each valid signal
transition whether the input capture flag (ICF) is set or clear. The input capture register always
TPG
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