Motorola GP2000, Руководство по обслуживанию, Страница: 68 / 102

7-6 Theory of Operation
3.5.3 Synthesizer
The frequency synthesizer is a large-scale monolithic synthesizer integrated circuit Q323 . The
synthesizer IC contains a dual modulus prescaler, programmable divide-by-N counter, prescale
control (swallow) counter, reference oscillator, reference divider, phase detector, charge pump and
lock detector. Also, included in
Q323 are shift registers and control circuits for frequency controls
and general device control.
RF output from the active VCO is AC coupled to the synthesizer Q323 prescaler input at Pin 8. The
divide counter chain in Q323 , consisting of the dual-modulus prescaler, swallow counter and
programmable counter, divides the VCO signal down to a frequency very close to 5.00kHz or
6.25kHz which is applied to the phase detector. The phase comparator compares the phase with
the 5.00kHz or 6.25kHz reference signal from the reference divider and drives the external charge
pump (
Q314 , Q315 and Q301 ). The synthesizer unlock detector circuit prevents the operation of the
transmitter and receiver, when the phase lock loop (PLL) is unlocked. The following discussion
assumes the unit has been placed in the transmit mode.
Q323 lock detector Pin 7 goes high when
the PLL is locked. This high level is applied to Pin 25 of the CPU Q101 . A software timing routing
brings the RX/TX line low (Pin 36 of Q101 ). With the RX/TX line goes low, Q209 is cut off and Q208
is biased on passing +5VTX-B to Q202 ; it biases on Q201 to pass switched TX-B to the transmitter
ampliÞer string which enables transmission.
When the PLL is unlocked, the lock detector at Q323 Pin 7 will begin pulsing low. A RC circuit
converts this low pulse to a low level for the CPU. The CPU then changes the RX/TX line to a high,
thus signaling the other transistor switches to drive
Q201 into cutoff, which disables transmission.
Therefore, the transmitter remains disabled while the loop remains out of lock, and "PLL ERR" is
displayed.
3.5.4 Loop Filter
The Loop Filter, a passive lead-lag Þlter consisting of R314 - R317 , R356 , C371 , C323 , and C369 ,
integrates the charge pump output to produce the DC turning voltage for the VCO. One parasitic
pole, consisting of RF chokes
L306 / L318 , prevent modulation of the VCOs by the 5.00kHz or
6.25kHz reference energy remaining at the output of the loop Þlter. Direct FM is obtained for
modulating frequencies outside the PLL bandwidth by applying the CTCSS/DCS signals and the
pre-emphasized, limited microphone audio to the VCO modulation circuit. The modulation circuit
consists of
R347 and Q329 .
3.6 Transmitter Section
3.6.1 RF Power AmpliÞer
After the PTT is pressed, the +5VTX-B line switches to approximately 5V. Q309 is turned on,
enabling transmit VCO. The VCO buffer, pre-driver, driver and power ampliÞer are biased on by
Q201 . Q201 is biased on by the +5VTX-B line switching to 5V. RF output from the transmit
VCO( Q325 ) is applied to the VCO output buffer Q308 . Output from Q308 feeds the buffer Q414 . The
output signal from Q414 feeds the pre-driver ampliÞer Q413 , and feeds the driver ampliÞer Q412 ,
whose output from the driver stage feeds the Þnal RF power ampliÞer Q411 to produce the rated
output power of 5 watts. The Þnal output is feed to a low-pass Þlter ( C446 - C448 , C451 , C452 , L418 ,
and L419 ) and then to the transmit/receive switch Q410 . RF power is then fed to the antenna via the
output low-pass Þlter consisting of C440 - C445 , L415 , and L416 .