Transmitter Power Amplifier (PA) 5-25W
3.1-28
Introduction/Theory of Operation
12.4
Antenna Switch
The antenna switch is switched synchronously with the K9V1 voltage along with the voltage PWR
CNTL signal and feeds either the antenna signal coming through the harmonic filter to the receiver
or the transmitter signal coming from the PA to the antenna via the harmonic filter.
In transmit mode, this PWR CNTL is above 1 V and biases Q3511 through Q3641 and Q3642 to
allow a collector current to be drawn. The collector current of Q3511 drawn from A+ flows via L3631,
L3531, L3532, L3533, directional coupler, D3551, L3651, D3651, L3652, R3645, R3646, L3641,
L3511 and switches the PIN diodes D3551 and D3651 to the low impedance state. D3551 leads the
RF signal from the directional coupler to the harmonic filter. The low impedance of D3651 is
transformed to a high impedance at the input of the harmonic filter by the resonant circuit formed by
L3651,C3652 and the input capacitance of the harmonic filter.
Transistor Q3643, controlled by the microprocessor via Signal K9V1, is used to switch the collector
current of Q3641 on in transmit mode and off in receive mode. In receive mode the low K9V1 and
the low PWR CNTL turn off the collector current of Q3511 through Q3641 and Q3642. With no
current drawn by Q3511 and resistor R3651 pulling the voltage at PIN diode D3651 to A+ both PIN
diodes are switched to the high impedance state. The antenna signal, coming through the harmonic
filter, is channelled to the receiver via L3651, C3651 and line PA RX. The high impedance of D3551/
D3651 in off state does not influence the receiver signal.
12.5
Harmonic Filter
The transmitter signal from the antenna switch is channelled through the harmonic filter to the
antenna connector J3501.The harmonic filter is formed by inductors L3551, L3552, and capacitors
C3551 through to C3554 This network forms a low-pass filter to attenuate harmonic energy of the
transmitter to specifications level. R3551 is used for electro-static protection.
12.6
Power Control
The power control loop regulates transmitter power with an automatic level control (ALC) loop and
provides protection features against excessive control voltage and high operating temperatures.
MOS FET device bias, power and control voltage limit are adjusted under microprocessor control
using a Digital to Analogue (D/A) converter (U0731). The microprocessor writes the data into the D/
A converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise
time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control
voltage.
The microprocessor controls K9V1 ENABLE (U0101-3) to switch on the first PA stage via transistors
Q0741, Q0742 and signal K9V1. The antenna switch is turned on by the collector current of the first
PA stage. PA DISABLE, also microprocessor controlled (U0101-34), sets BIAS VLTG (U0731-4) and
VLTG LIMIT SET (U0731-13) via Q0731, D0731 in receive mode to low to switch off the bias of the
MOS FET device Q3521 and to switch off the power control voltage (PWR CNTL).
Through an Analogue to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA
control voltage (PWR CNTL) during the tuning process.
Содержание GM1200E
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