
Reset
Technical Summary
2-9
2.7 Reset
Logic is provided on the DSP56F801 to generate a clean Power-On RESET signal.
Additional, reset logic is provided to support the RESET signals from the JTAG
connector, the Parallel JTAG Interface and the user RESET push-button; refer to
Figure 2-6. Block Diagram of the RESET Interface
RESET
PUSHBUTTON
MANUAL RESET
P_RESET
RESET
+3.3V
Содержание DSP56F801
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