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MOTOROLA Optimizing DSP56300/DSP56600 Applications 3-1
This section
discusses
important program
control features
and new additions.
Section 3
PROGRAM CONTROL
3.1 HARDWARE LOOPS
Hardware looping is one of the strongest features of the
DSP56300/DSP56600 core families. Loop counter management and
end-of-loop testing is done by hardware in parallel to instruction
execution, thus saving execution time of otherwise needed control
software. This enables the user to muster more performance in
critical loops, and also makes program writing more close to
high-level languages. Consider the following C code example:
for (i = 0; i < 100; i++){
a = a + data[i];
}
A straight forward assembly implementation of the main loop of the
code may look like this:
move #MEMORY_AREA,r0
clr a #100,b
move x:(r0)+,x0
_LOOP_TOP
add x0,a x:(r0)+,x0
sub #1,b
tst b
jne _LOOP_TOP
Using hardware looping, this code looks like:
move #MEMORY_AREA,r0
clr a x:(r0)+,x0
do #100,_LOOP_END
add x0,a x:(r0)+,x0
_LOOP_END
There is more to hardware loops than easy programming. The loop
control hardware is optimized for maximum pipeline efficiency.
There is no stall between loop iterations; all comparisons and loop
counter arithmetic are done in parallel to instruction execution. It is
important to know that after the loop is initialized (execution of the
DO instruction), the instructions in the loop are fetched and
executed in sequence. From the pipeline’s point of view, there is no
difference between the code in the last example and the “ADD”
instruction written 100 times in sequence.