Motorola CPCI-9120, Справочное руководство

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PHY Reset Control Register
Address: C600 3020
Type: Read/Write
This register provides a means of controlling PHY operation. The PHY can be held in reset
until the OS is ready to initialize the PHY. This delayed reset is useful in cases where it is nec-
essary to prevent link-pulses from being sent on the line before the OS has booted (Example:
Rev C0 silicon of Marvell’s 88E1145).
MUX Control Register
Address: C600 3040
Type: Read/Write
This register controls the flow of Ethernet signals between the RTB and PSB.
Figure 29:
Board revision Number
Bit Description Access
3:0 Board Revision number for the current board RO
Table 36:
PHY Reset Control Register
Bit Description Access
0 0: Quad PHY Reset is asserted
1: Quad PHY Reset is de-asserted
Reset value: 0 R/W
Figure 30:
Mux Control Register
Bit Description Access
1:0 01: Port0 and Port2 of the Quad PHY are routed to RTB
Port0 and Port1 of the 82546 are routed to PSB
10: Port0 and Port2 of the Quad PHY are routed to PSB
00,11: Reserved
Reset value: 01 R/W