Mitsubishi Electric DD-5000, Руководство по обслуживанию, Страница: 54 / 76

3-34
Table 3-5-10 (3/5) TMP94CS40AF Table 3-5-10 (4/5) TMP94CS40AF
Pin
No.
14
15
16
24
25
26
27
28
29
152
|
159
6
7
8
9
10
31
32
4
5
43
48
36
38
40
Function
Port E4: I/O port.
Timer output A: 16 bit timer A is developed.
Port E5: I/O port.
Timer input A: 16 bit timer A is entered.
Interrupt request terminal A: programmable
at rising/falling edges.
Port E6: I/O port.
Timer input B: 16 bit timer A is entered.
Interrupt request terminal B: Interrupt
request terminal at rising edge.
Port F0: I/O port.
Serial transfer data 0 (open drain output
capability)
Port F1: I/O port.
Serial reception data 0
Port F2: I/O port.
Serial transfer capability 0
Serial clock I/O 0
Port F4: I/O port.
Serial transfer data 1 (open drain output
capability)
Port F5: I/O port.
Serial reception data 1
Port F6: I/O port.
Serial transfer capability 1
Serial clock I/O 1
Analog input: input of 10 bit A/D converter.
Port H0: I/O port.
Terminal count 0: Strobe output signal is
developed at “H” level when count value of
micro DMA channel 0 is 0.
Port H1: I/O port.
Terminal count 1: Strobe output signal is
developed at “H” level when count value of
micro DMA channel 1 is 0.
Port H2: I/O port.
Terminal count 2: Strobe output signal is
developed at “H” level when count value of
micro DMA channel 2 is 0.
Port H3: I/O port
Terminal count 3: Strobe output signal is
developed at “H” level when count value of
micro DMA channel 3 is 0.
Port H4: I/O port (schmitt input)
Interrupt request terminal 0: programmable
at level/rising edge. (Schmitt input)
Nonmaskable interrupt request terminal:
interrupt request terminal at falling edge.
Available at rising edge by using a program.
Watchdog timer output terminal
Address mode: selects start-up external
data bus width after releasing reset.
AM1= “0” AM0= “0”:
starts with 8 bit external data bus
AM1= “0” AM0= “1”:
starts with 16 bit external data bus
AM1= “1” AM0= “0”:
starts with 32 bit external data bus
AM1= “1” AM0= “1”:
starts from internal ROM
Test: used with “GND” fixed.
Clock: develops system clock.
Oscillation connection terminal
Name
P E 4
TOA
P E 5
TIA
INTA
P E 6
TIB
INTB
PF0
TXD0
PF1
R X D 0
PF2
C T S 0
SCLK0
PF4
TXD1
PF5
R X D 1
PF6
C T S 1
SCLK1
AN0 – AN7
PH0
TC0
PH1
TC1
PH2
TC2
PH3
TC3
PH4
INT0
NMI
WDTOUT
AM0,1
TEST0,1
C L K
X1/X2
Pin
No.
55
54
53
52
51
140
141
17
18
19
20
21
22
24
25
13
Function
Port B0: output port. (Initializes to “1” output.)
Column address strobe 1: CAS strobe
signal for DRAM is developed if address is
within the assigned address range.
Lower column address strobe 1: lower CAS
strobe signal for DRAM is developed if
address is within the assigned address
range.
Lower-lower column address strobe 1:
lower-lower CAS strobe signal for DRAM is
developed if address is within the assigned
address range.
Port B1: output port. (Initializes to “1” output.)
Upper column address strobe 1: upper CAS
strobe signal for DRAM is developed if
address is within the assigned address
range.
Lower-upper column address strobe 1:
lower-upper CAS strobe signal for DRAM is
developed if address is within the assigned
address range.
Port B2: output port. (Initializes to “1” output.)
Upper-lower column address strobe 1:
upper lower CAS strobe signal for DRAM is
developed if address is within the assigned
address range.
Port B3: output port. (Initializes to “1” output.)
Upper-upper column address strobe 1:
upper-upper CAS strobe signal for DRAM is
developed if address is within the assigned
address range.
Port B4: output port. (Initializes to “1” output.)
Write enable 1: write enable signal for
DRAM is developed.
Port C0: I/O port.
Timer output 1: 8 bit timer 0 or timer 1 is
developed.
Timer output 7: 16 bit timer 7 is developed.
Port C1: I/O port.
Timer output 3: 8 bit timer 2 or timer 3 is
developed.
Timer output B: 16 bit timer B is developed.
Port D0: I/O port.
Timer output 4: 16 bit timer 4 is developed.
Port D1: I/O port.
Timer input 4: 16 bit timer 4 is entered.
Interrupt request terminal 4: programmable
at rising/falling edges.
Port D2: I/O port.
Timer input 5: 16 bit timer 4 is entered.
Interrupt request terminal 5: Interrupt
request terminal at rising edge.
Port D4: I/O port
Timer output 6: 16 bit timer 6 is developed.
Port D5: I/O port.
Timer input 6: 16 bit timer 6 is entered.
Interrupt request terminal 6: programmable
at rising/falling edges.
Port D6: I/O port.
Timer input 7: 16 bit timer 6 is entered.
Interrupt request terminal 7: Interrupt
request terminal at rising edge.
Port E0: I/O port.
Timer output 8: 16 bit timer 8 is developed.
Port E1: I/O port.
Timer input 8: 16 bit timer 8 is entered.
Interrupt request terminal 8: programmable
at rising/falling edges.
Port E2: I/O port.
Timer input 9: 16 bit timer 8 is entered.
Interrupt request terminal 9: Interrupt
request terminal at rising edge.
Name
PB0
C A S 1
LCAS1
LLCAS1
PB1
U C A S 1
LUCAS1
PB2
HLCAS1
PB3
HUCAS1
PB4
W E 1
P C 0
TO1
TO7
P C 1
TO3
TOB
PD0
TO4
PD1
TI4
INT4
PD2
TI5
INT5
PD4
TO6
PD5
TI6
INT6
PD6
TI7
INT7
P E 0
TO8
P E 1
TI8
INT8
P E 2
TI9
INT9