80
80
80
50QMA
50QMA
N/B Maintenance
N/B Maintenance
5.1 Intel 915PM North Bridge(3)
DDR / DDR2 SDRAM Channel A Interface
Signal Name
Type
Description
SA_DQ[63:0]
I/O
SSTL1.8/2
2x
Data Bus:
DDR / DDR2 Channel A data signal interface to the SDRAM data
bus.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SA_DM[7:0]
I/O
SSTL1.8/2
2x
Data Mask:
These signals are used to mask individual bytes of data in the case of
a partial write, and to interrupt burst writes.
When activated during writes, the corresponding data groups in the
SDRAM are masked. There is one SA_DM[7:0] for every data byte
lane.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SA_DQS[7:0]
I/O
SSTL1.8
2x
Data Strobes:
DDR: The rising and falling edges of SA_DQS[7:0] are used for
capturing data during read and write transactions.
DDR2: SA_DQS[7:0] and its complement signal group make up a
differential strobe pair. The data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS[7:0]# during read and write
transactions.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SA_DQS[7:0]#
I/O
SSTL1.8
2x
Data Strobe Complements
DDR1: No Connect. These signals are not used for DDR devices
DDR2 : These are the complementary DDR2 strobe signals.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SA_MA[13:0]
O
SSTL1.8/2
Memory Address:
These signals are used to provide the multiplexed row and column
address to the SDRAM.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Note: SA_MA13 is for support of 1 Gb devices.
SA_BS[2:0]
O
SSTL1.8/2
Bank Selec
t:
These signals define which banks are selected within each SDRAM
rank.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Note: SA_BS2 is for support for DDR2 only for 8 bank devices.
DDR / DDR2 SDRAM Channel A Interface (Continued)
Signal Name
Type
Description
SA_RAS# O
SSTL1.8/2
RAS Control signa
l:
Used with SA_CAS# and SA_WE# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SA_CAS# O
SSTL1.8/2
CAS Control signal:
Used with SA_RAS# and SA_WE# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SA_WE# O
SSTL1.8/2
Write Enable Control signal:
Used with SA_RAS# and SA_CAS# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SA_RCVENIN#
O
SSTL1.8/2
Clock Input:
Used to emulate source-synch clocking for reads. Connects internally
to SA_RCVENOUT#.
Leave as No Connect.
SA_RCVENOUT
#
O
SSTL1.8/2
Clock Output:
Used to emulate source-synch clocking for reads. Connects internally
to SA_RCVENIN#.
Leave as No Connect.
PCI Express Based Graphics Interface Signals
Signal Name
Type
Description
EXP_RXN[15:0]
EXP_RXP[15:0]
I
PCIE
PCI Express Receive Differential Pair
EXP_TXN[15:0]
EXP_TXP[15:0]
O
PCIE
PCI Express Transmit Differential Pair
EXP_ICOMPO
I
A
PCI Express Output Current and Resistance Compensation
EXP_COMPI
I
A
PCI Express Input Current Compensation
PCI Express Based Graphics is supported for Intel 915GM and Intel 915PM chipsets.
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