RTE-V830-PC
USER’ S MANUAL
40
11.14. 16-BIT BUS MODE (SINGLE WRITE)
The byte-unit or halfword-unit single write access in the 16-bit bus mode is the same as that in
the 32-bit bus mode. The word-unit single write access in the 16-bit bus mode behaves
similarly to the burst mode, and differs from that in the 32-bit bus mode.
The following timing chart shows the waveforms that occur when a row address in a word-unit
single write cycle during the 16-bit bus mode matches (hit) a row address used in the previous
cycle. This timing chart applies to both the interleave and noninterleave modes.
For a row address that does not match the one in the previous cycle (mishit) or for the first cycle
after a refresh cycle, the single write cycle in the 16-bit bus mode is the same as that in the
32-bit bus mode. See the descriptions about the single write cycle in the 32-bit bus mode.
²
The waveform width indicated as Nclk (*1) in the timing chart corresponds to the number of
clock cycles in the write CAS width (1 or 2) to be specified for the port. The minimum
cycle is in the 2-2 format.
²
The RAS- signal is kept at a low level for page mode access even after the end of the cycle.
(*2)
²
The CASL- and CASH- signal, whichever corresponds to the appropriate byte position in
the appropriate bank, becomes active according to the state of A2 and bus enable signals
BE0- to BE3-. (*3)
²
Write data in the first cycle is through-latched at the DRAM control circuit so that it can be
written on a single CAS signal.
WE-
CASH-
CASL-
*4
*3
*3
*2
Low
Nclk
*1
Nclk
*1
RAS-
Sig1: A2 to A27, BE0- to BE3-, ST0 to ST3
D0 to D15
Sig1
READY-
BCYST-
BCLK
HIT
Nclk
*1
Nclk
*1
