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RTE-V830-PC

USER’ S MANUAL

30

11.5.  32-BIT BUS MODE (SINGLE READ, NOHIT)

The following timing chart shows the waveforms that occur when a row address to be accessed

in a single read cycle during the 32-bit bus mode does not match (nohit) a row address used in

the previous cycle.

²

 

The waveform widths indicated as Lclk (*1), Mclk (*2), and  Nclk (*3) in the timing chart

correspond to the number of clock cycles in the precharge width (1 to 3), RAS width (2 to 4),

and read CAS width (1 to 3) to be specified for the port.  The minimum cycle is three wait

states.

²

 

The RAS- signal is kept at a low level for page mode access even after the end of the cycle.

(*4)

²

 

The upper and lower 32-bit banks are read simultaneously.  The CPU is supplied with

data from an appropriate bank according to the state of A2.

WE-

CASH-

CASL-

*4

Low

Nclk

*3

HIT

RAS-

Sig1:  A2 to A27, BE0- to BE3-, ST0 to ST3

Sig1

D0 to D31

READY-

BCYST-

BCLK

Mclk

*2

Lclk

*1

Содержание RTE-V830-PC

Страница 1: ...RTE V830 PC User s Manual Midas lab...

Страница 2: ...Correction of error in which SW1 was written as SW2 and vice versa Correction of error related to descriptions about SW1 1 2 and 3 4 settings February 5 1996 0 92 14 Correction of errors in tables in...

Страница 3: ...3 8 CPU TEST PINS J1 8 3 9 CLOCK SOCKET OSC1 8 3 10 DRAM SIMM SOCKETS 9 3 11 ROM SOCKETS 9 4 INSTALLATION AND USE 10 4 1 BOARD SETTING 10 4 2 INSTALLATION ON THE ISA BUS 11 4 3 STANDALONE USE OF THE...

Страница 4: ...9 11 5 32 BIT BUS MODE SINGLE READ NOHIT 30 11 6 32 BIT BUS MODE SINGLE WRITE NORMAL 31 11 7 32 BIT BUS MODE SINGLE WRITE HIT 32 11 8 32 BIT BUS MODE SINGLE WRITE NOHIT 33 11 9 32 BIT BUS MODE BURST R...

Страница 5: ...its using local bus connectors provided on the evaluation board 1 1 NUMERIC NOTATION This manual represents numbers according to the notation described in the following table Hexadecimal and binary nu...

Страница 6: ...es ROM 256 Kbytes 64K x 16 bit EPROM x 2 SRAM 512 Kbytes 64K x 16 bit SRAM x 4 DRAM 8 16 or 32 Mbytes standard of 8 Mbytes installed in two 72 pin SIMM sockets RS 232C port 9 pin D SUB connector Commu...

Страница 7: ...rated as listed below Voltage 5 V Current Maximum of 2 A excluding the current supplied to the JEXT connector Mating connector Type A 5 5 mm in diameter Polarity GND GND 5V 5V Caution When attaching...

Страница 8: ...he CPU is active low CS3 Lights when the CS3 pin of the CPU is active low TOVER Lights when a time out occurs LED Indication 3 6 TEST PINS TP Test pins are used to connect a ROM in circuit debugger Th...

Страница 9: ...7 RTS RS Output 8 5 8 CTS CS Input 7 4 9 NC JSIO Connector Signals 3 8 CPU TEST PINS J1 The CPU test pins are connected to the corresponding CPU pins The test pin numbers correspond to the CPU pin nu...

Страница 10: ...the capacity of DRAM Select SIMM chips that meet the access timing requirements listed in a table elsewhere The selected SIMM chips must be of the same model The capacity of installed SIMMs can be de...

Страница 11: ...o 8 correspond to ISA addresses A4 to A11 respectively A12 to A15 are fixed at 0 This means that the I O address that can be selected ranges between 000xH and 0FFxH When a switch contact is open it co...

Страница 12: ...of the PC using a DIP switch on the board Be careful not to specify the same I O address as used for any other I O unit See Section 4 1 for switch setting Turn off the power to the PC open its housing...

Страница 13: ...ure Get an RS 232C cable for connection with the host and an external power supply 5 V 1 A on hand Especially for the power supply watch for its voltage and connector polarity In addition attach space...

Страница 14: ...S1 space CS2 space CS3 space 7000 0000 7DFF FFFF 5FFF FFFF 5000 0000 6000 0000 6FFF FFFF 7FFF FFFF Access inhibited Access inhibited Access inhibited FDFF FFFF FE00 0000 FE00 0FFF CS0 space Built in i...

Страница 15: ...Its capacity is 512 Kbytes SRAM can be accessed with no wait state Wait states can be specified for read and write cycles separately See Section 6 2 ROM space FFFC 0000H to FFFF FFFFH and 7FFC 0000H t...

Страница 16: ...MR1 MR2 MR1 MR2 6100 0404h SR CSR 6100 0408h Reserved CR 6100 040Ch RHR THR 6100 0410h Reserved ACR 6100 0414h ISR IMR 6100 0418h CTU CTUR 6100 041Ch CTL CTLR SCC2691 Register Mapping The general pur...

Страница 17: ...bit specifies whether to use the noninterleave emulation mode When the bit is 1 the DRAM is put in the normal mode When it is 0 the DRAM is put in the noninterleave emulation mode SRAMWRWIDE1 0 These...

Страница 18: ...four CPU bus clock cycles 1 0 1 This bit combination shall not be specified 1 1 0 This bit combination shall not be specified 1 1 1 This bit combination shall not be specified WRCASWIDE0 This bit spec...

Страница 19: ...used to mask an NMI signal input to the CPU When the bit is 1 the NMI signal is masked at a gate The bit should be initialized to 1 When an NMI becomes acceptable the bit should be reset to 0 In the M...

Страница 20: ...1 P10 DPseg Gseg Fseg Eseg Dseg Cseg Bseg Aseg Port 4 DIP SW1 state read port input 61000C04h P17 P16 P15 P14 P13 P12 P11 P10 SW1 8 SW1 7 SW1 6 SW1 5 SW1 4 SW1 3 SW1 2 SW1 1 SIZE16B CMODE no use no us...

Страница 21: ...ate ON ON No timer is used ON OFF 200 Hz 5 ms OFF ON 100 Hz 10 ms OFF OFF 60 Hz 16 67 ms CMODE The multiplication factor for the internal clock frequency triple for ON and double for OFF SIZE16B Bus s...

Страница 22: ...ress bus signal which is originally the CPU address signal received at a buffer BHE Output Byte high enable signal which is originally the CPU UBE signal received at a buffer D 0 15 Input output Data...

Страница 23: ...me 15 T6 RD data hold time 0 T7 RD READY WAIT setup time 0 T8 RD READY setup time 0 T9 RD READY hold time 0 T10 WR address setup time 0 T11 WR address hold time 20 T12 WR cycle time 50 T13 WR cycle in...

Страница 24: ...TR of the SCC2691 becomes active an NMI occurs see Section 6 1 NMI request from a TP A reset occurs when the NMI test pin receives an input See Section 3 6 for details Request from the ISA bus An NMI...

Страница 25: ...07 FFFFH 9 2 INTERRUPTS When running on the Multi monitor user programs cannot use interrupts at present 9 3 _INIT_SP SETTING _INIT_SP stack pointer initial value is set to FE06 FFFCH highest SRAM add...

Страница 26: ...e invalid 0x1234 1234H 1234 10 1 HELP Format HELP command name Displays a list of RTE commands and their formats A question mark can also be used in place of the character string HELP If no command na...

Страница 27: ...bit is on are displayed except when ALL is specified If ALL is specified the contents of all DCTR registers are displayed The DCTR registers are mapped on the I O space f2000000h f2000fffh 10 7 ITCR...

Страница 28: ...NAL DESCRIPTIONS The signals used for waveforms described in this chapter are defined as follows BCLK Bus clock pulse input to the CPU BCYST Bus cycle start signal output from the CPU READY Ready sign...

Страница 29: ...ths indicated as Mclk 1 and Nclk 2 in the timing chart correspond to the number of clock cycles in the RAS width 2 to 4 and read CAS width 1 to 3 to be set for the port respectively The minimum cycle...

Страница 30: ...k 1 in the timing chart corresponds to the number of clock cycles in the read CAS width 1 to 3 to be specified for the port The minimum cycle is one wait state The RAS signal is kept at a low level fo...

Страница 31: ...ng chart correspond to the number of clock cycles in the precharge width 1 to 3 RAS width 2 to 4 and read CAS width 1 to 3 to be specified for the port The minimum cycle is three wait states The RAS s...

Страница 32: ...and Nclk 2 in the timing chart correspond to the number of clock cycles in the RAS width 2 to 4 and write CAS width 1 or 2 to be set for the port respectively The minimum cycle is one wait state The...

Страница 33: ...corresponds to the number of clock cycles in the write CAS width 1 or 2 to be specified for the port The minimum cycle is one wait state The RAS signal is kept at a low level for page mode access eve...

Страница 34: ...o the number of clock cycles in the precharge width 1 to 3 RAS width 2 to 4 and write CAS width 1 or 2 to be specified for the port The minimum cycle is three wait states The RAS signal is kept at a l...

Страница 35: ...t is the same as in the single read cycle See the descriptions about the single read cycle The waveform width indicated as Nclk 1 in the timing chart corresponds to the number of clock cycles in the r...

Страница 36: ...the single write cycle See the descriptions about the single write cycle The waveform width indicated as Nclk 1 in the timing chart corresponds to the number of clock cycles in the write CAS width 1 o...

Страница 37: ...nning section of the cycle differs from the one shown in the following timing chart It is the same as in the single read cycle See the descriptions about the single read cycle The waveform width indic...

Страница 38: ...ion of the cycle differs from the one shown in the following timing chart It is the same as in the single write cycle See the descriptions about the single write cycle The waveform width indicated as...

Страница 39: ...revious cycle mishit or for the first cycle after a refresh cycle the single read cycle in the 16 bit bus mode is the same as that in the 32 bit bus mode See the descriptions about the single read cyc...

Страница 40: ...RTE V830 PC USER S MANUAL 39 WE CASH CASL 2 Low Nclk 1 RAS Sig1 A2 to A27 BE0 to BE3 ST0 to ST3 D0 to D15 Sig1 READY BCYST BCLK HIT Nclk 1...

Страница 41: ...ycle the single write cycle in the 16 bit bus mode is the same as that in the 32 bit bus mode See the descriptions about the single write cycle in the 32 bit bus mode The waveform width indicated as N...

Страница 42: ...e one in the 32 bit bus mode See the descriptions about the single read cycle in the 32 bit bus mode The waveform width indicated as Nclk 1 in the timing chart corresponds to the number of clock cycle...

Страница 43: ...descriptions about the single write cycle in the 32 bit bus mode The waveform width indicated as Nclk 1 in the timing chart corresponds to the number of clock cycles in the write CAS width 1 or 2 to b...

Страница 44: ...h cycle only the beginning section of the cycle differs from that in the 32 bit bus mode See the descriptions about the single read cycle in the 32 bit bus mode The waveform width indicated as Nclk 1...

Страница 45: ...the beginning section of the cycle differs from that in the 32 bit bus mode See the descriptions about the single write cycle in the 32 bit bus mode The waveform width indicated as Nclk 1 in the timi...

Страница 46: ...RTE V830 PC USER S MANUAL 45 Memo RTE V830 PC User s Manual M471MNL02 Midas lab...

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