Microwave Data Systems MDS 4310, Установка, эксплуатация и техническое обслуживание на месте

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A-2 APPENDIX A MDS 05-2415A01, Rev. A
THEORY OF OPERATION
(Refer to Figure A-1 and Figure A-2)
Modulator
The modulator consists of a monolithic function generator integrated circuit, U2, which
generates an audio tone whose frequency depends on the state of Pin 9, the data input. A
voltage-controlled oscillator is included in the IC, the frequency of which is determined by
either R2 or R3. When Pin 9 is high, R2 and C3 determine the frequency of oscillation. When
Pin 9 is pulled low, R3 and C3 control the frequency of the oscillator, whose output appears
at Pin 2 of U2.
Normally, for operation in the Bell 202 format, R2 is adjusted to produce a 1200 Hz “mark”
tone and R3 is set for a 2200 Hz “space” tone. Transmit data is supplied to Pin 9 of U2.
Demodulator
U5 is a phase-locked loop (PLL) FSK demodulator. Frequency-shifted audio from the radio
receiver is applied at Pin 2, which is one input of a phase detector. The other input to the
phase detector is the internal voltage-controlled oscillator (VCO), the frequency of which is
determined by C29 and R25. An error voltage is developed by the phase detector when the
incoming audio signal frequency differs from the VCO frequency. This error voltage is
applied to a comparator, whose output is the recovered data information.
A lock detect signal is also derived from the PLL circuit, and this is used to provide a data
carrier detect (DCD) logic signal to the RTU.
Keyline (PTT) Dropout Delay
In order to prevent possible data errors from a noise burst at the termination of the transmit
modulation tone, U3 provides a supervisory control of the data modulator, U2. U3 makes
sure the Data Modulator is turned off at the end of a data transmission only when the
modulating signal has reached the zero or cross-over point.