VSC8584 Evaluation Board
VPPD-03500 VSC8584 User Guide Revision 1.0
3
3
General Description
The evaluation board in Figure 1 provides the user a way to evaluate the VSC8584 device in multiple
configurations. Four RJ-45 connectors are provided for copper media interfaces. The four SFP cages
allow for evaluation of the fiber media interconnects. The MAC interface is provided via SMA
connectors.
For access to all of the features of the device, an external microcontroller is used to configure the on-
board clock chip via a two-wire serial bus and the VSC8584 via the MDIO bus. The graphical user
interface (GUI) enables the user to access the registers.
The evaluation board uses a Zarlink device to synthesize a 125 MHz reference clock signal from a 20
MHz crystal which serves as the REFCLK input.
3.1
Key Features
3.1.1
Copper Port RJ45 Connections
PHY Ports 2 and 3 use UDE RTA 1648BAK1A with integrated magnetic while PHY Ports 0 and 1 use
generic RJ45 connectors with discrete Pulse H5008 magnetics.
3.1.2
SGMII/QSGMII MAC SMA
SGMII SMA connections are provided for all PHYs while the QSGMII SMA connection is available only on
PHY0.
3.1.3
Switch Block Control
Set the SW1 switch as shown in the figure below.
Figure 2 • SW1 Switch Control
3.1.4
Zarlink ZL30343 SyncE G.8262/SETS
The Zarlink ZL30343 is initialized by default to provide a 125 MHz differential LVPECL clock to VSC8584
REFCLK inputs. (Note: the ZL30343 can be programmed to provide LVDS differential clock in conjunction
with an LVDS termination provided for REFCLK, please refer to the Zarlink manual for programming its
output drive).
Also, the ZL30343 can support synchronization with the VSC8584 PHY recovered clock for SyncE
operation. The ZL30343 is initialized to lock a recovered clock output if one is enabled and available
from the VSC8584 PHY. If no recovered clock signal is available, then the ZL30343 will select the crystal
oscillator (U16) as default reference source for holdover operation. ZL30343 will indicate locked versus
holdover status by driving LED D33 or D34. See the Zarlink documentation for more discussion
concerning its operation. See the VSC8584 datasheet for configuring recovered clock output pin
behavior.
Please ensure three-way resistive connections R19 and R22 are appropriately connected to feedback the
VSC8584’s recovered clock outputs into the ZL30343 device, if synchronization to a recovered clock
source is desired.
