Board Components and Operations
UG0786 User Guide Revision 1.0
11
The following figure shows the SPI Flash interface of the PolarFire Splash Board.
Figure 5 •
SPI Flash Interface
For more information, see the Board Level Schematics document (provided separately).
4.3
Transceivers
The PolarFire MPF300TS-1FCG484EES device has eight transceiver lanes, which can be accessed
through the PCIe Edge connectors and FMC LPC connectors on the board.
4.3.1
XCVR0 Interface
The XCVR0 interface has four lanes connected as follows:
•
Lanes 0, 1, 2, and 3 are directly routed to the PCIe connector:
•
TX pad > trace > AC coupling > trace > via (to bottom layer) > trace > PCIe connector pad
•
RX pad > trace > via (to top layer) > trace > PolarFire device pad
The XCVR0 reference clock is routed directly from the PCIe connector to the PolarFire device.
The XCVR0 TXD pairs are capacitively coupled to the PolarFire device. Serial AC-coupling capacitors
are used to provide common-mode voltage independence.
The following figure shows the XCVR0 interface of the PolarFire Splash Board.
Figure 6 •
XCVR0 Interface
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