Hardware Components
UG0048 User Guide Revision 5.1
9
Using FlashPro software, program the example design on ProASIC3/E device.
3.5.3
Jumpers for Isolating Switches and LEDs from FPGA
Many jumpers are provided on the board to allow the user to disconnect various switch combinations or
LEDs from the FPGA I/O banks. All such jumpers are shown in the schematic in
are labeled on the top-layer silkscreen as JP* where * is a number. All jumpers are also labeled with the
FPGA I/O pin number to which they are connected; example, JP48 for the 3.3 V connection of VPUMP to
the FPGA is labeled with 106, which indicates that it is connected to pin 106. Similarly, SW4 has a jumper
above it called JP14, which is labeled with 64, indicating that SW4 is connected through to pin 64 of the
FPGA when this jumper is in place.
Disconnecting the jumpers JP11, JP12, JP13, and JP14 causes the momentary push-button switches
(SW1, SW2, SW3, and SW4) to be disconnected from the FPGA so that the I/O pins 68, 67, 66, and 64
are used for other purposes. Disconnecting the eight jumpers, JP1 through JP8, causes the eight light
emitting diodes (D1 through D8) to be disconnected from the FPGA I/O pins 63, 61, 60, 59, 58, 57, 56,
and 55, respectively.
The momentary push-button switches (SW5 and SW6, for applying a reset pulse and a global pulse) are
connected through jumpers JP15 and JP16 to I/Os 159 and 113 respectively. All labeling is clearly shown
on the silk screen.
The hex switches U13 and U14 each are connected to four I/Os on the FPGA. There are four separate
jumpers for each of these hex switches, located on the bottom right of the board. They are labeled with
Bit0, Bit1, Bit2, and Bit3 on the silk screen, as well as being labeled with the I/O pin on the FPGA to
which each is connected.
This allows individually control the desired effect of a switch and, by connecting directly to the FPGA side
of a disconnected jumper, hold a particular pin at a chosen logic level while continuing to use the hex
switch to affect other pins. This flexibility is useful for experimentation with designs of your own choosing
and connecting other external equipment to the board for development purposes.
The internal and external oscillator selection through JP24 is worth a mention. JP24 is a three-pin header
onto which a normal two-hole shunt is fitted. Normally, the shunt is connected across pins 3 and 2 of
JP24. In this position the on-board oscillator, U1, provides the internal clock to the middle pin of the
jumper which in turn is connected to pin 26 of the FPGA. By moving the shunt down to connect pins 2
and 1 of JP24, the external clock at pin 1 is connected to the FPGA instead. The external clock is
connected through the SMA connector J19 at the bottom left of the board.
The following table lists the jumpers available on the board with their description.
Table 2 •
Summary of Jumpers
Jumper
Description
JP1 to JP8
To connect LEDs (LED1 to LED8) to FPGA
JP10
VJTAG enable/disable
JP11 to JP14
To connect push-button switches (SW1, SW2, SW3, and SW4) to FPGA
JP15 and JP16
To connect momentary push-button switches SW5 and SW6 to FPGA
JP9 and JP17 to JP19
To connect hex switch (U13) to FPGA
JP20 to JP23
To connect hex switch (U14) to FPGA
JP24
On-board or external clock source selection
JP48
VPUMP voltage
JP49
VCCPLC – Power supply to the east side PLL
JP50
VCCPLF – Power supply to the west side PLL
Содержание ProASIC3/E Proto Kit
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