3 – Key Components Description and Operation
22
IGLOO2 FPGA Evaluation Kit User Guide
System Reset
The DEVRST_N signal (active low) is asserted, if the power supply level 3.3 V or 1.2 V fall below the threshold level
or by pressing the SW6 (push-button switch). DEVRST_N is an input-only reset pad that allows assertion of a full
reset to the chip at any time.
IGLOO2 FPGA
DEVRST_n
DS1818
Reset
10K
1uF
3.3V
Push button switch
3.3 V
SW6
U3
TPS3808G09
1.2 V
Reset
Sense
Figure 13.
System Reset Interface
Note:
For more information, refer to page 13 of Board Level Schematics document (provided separately).
Clock Oscillator
50 MHz Clock Source
Figure 14
shows the 50 MHz clock oscillator with +/-50 ppm is available on the board. This clock oscillator is
connected to the FPGA fabric to provide a system reference clock.
An on-chip IGLOO2 PLL can be configured to generate a wide range of high precision clock frequencies.
Table 8.
50 MHz Clock
IGLOO2 Dev Kit
IGLOO2- Pkg No
IGLOO2 Pin Name
50MHZ_ SECLK_ WST_K1
K1
MSIOD85PB6/CCC_NE1_CLKI1
Osc- 50MHz
IGLOO2 FPGA
GND
TRISTATE
VDD
OUT
2P5V
50MHZ_ SECLK_ WST_K1
Figure 14.
Clock Oscillator Interface
Note:
For more information, refer to page 6 of Board Level Schematics document (provided separately).