3 – Key Components Description and Operation
IGLOO2 FPGA Evaluation Kit User Guide
17
IGLOO2
FPGA
SERDES0
RXD1
TXD0
TXD1
RXD0
REF CLK1P
Loopback
RXD3
TXD3
RXD2
TXD2
REF CLK1N
REF CLK0
PCIe
Connector
Marvell
PHY
Marvell
PHY
On board
Oscillator
MUX Circuit
3.3 V
A
B
MUX
O/Ps
SMA
Lane1
Lane0
Lane2
Lane3
SMA
O/P Sel
MUX Sel
J23
J22
3.3 V
Figure 8.
SERDES0 Interface
For more information on J22 and J23 jumpers, refer to
Table 4
.
Note:
•
SERDES0 TXD pairs are capacitively coupled to the IGLOO2 device. Series AC coupling capacitors are used to
provide Common mode voltage independence.
•
The AC coupling capacitors are not provided for SERDES 0 RXD signals. The mating board should have the AC
coupling capacitors.
•
For more information, refer to page 4 of Board Level Schematics document (provided separately).