IGLOO nano Starter Kit
R e v i s i o n 3
11
FPGA Description: AGLN250V2-VQG100
This IGLOO nano board is populated with an IGLOO nano AGLN250V2-VQG100 FPGA. An IGLOO
nano AGLN250 FPGA supports the enhanced nano features of Schmitt Trigger input, bus hold (holds
previous I/O state in Flash*Freeze mode), cold-sparing, hot-swap I/O capability, and 1.2 V programming.
In Designer, users can target their design to use either IGLOO AGL250 or IGLOO nano AGLN250. Some
features are listed in the
section and
. Refer to the
for
additional features.
Key Features
•
Ultra-low power in Flash*Freeze mode
•
Enhanced commercial temperature
•
Reprogrammable flash technology
•
1.2 V to 1.5 V single voltage operation
•
Enhanced I/O features
•
Selectable Schmitt trigger Inputs
•
Clock conditioning circuits (CCCs) and integrated PLLs
•
Embedded SRAM and nonvolatile memory (NVM)
•
In-system programming (ISP) and security
For further information, refer to the IGLOO nano datasheet:
www.microsemi.com/soc/documents/IGLOO_nano_DS.pdf
.
Table 1-2 • Features of AGLN250V2-VQG100
Component
Specification
System Gates
250,000
Typical Equivalent Macrocells
2,048
VersaTiles (D-flip-flops)
6,144
Flash*Freeze Mode (Typical, µW)
24
RAM kbits (1,024 bits)
36
4,608-Bit Blocks
8
FlashROM (bits)
1,024
Secure (AES) ISP
Yes
Integrated PLLs in CCCs
1
VersaNet Globals
18
I/O Standards
Std. or Hot-Swap
I/O Banks
4
Speed Grades
Std.
Temperature Grade
C, I
Single-Ended I/Os
68
Содержание IGLOO nano Starter Kit
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