_________________________________________________________________________________________ DS3106DK
11
DFS are configured for programmable DFS operation, the
DIG1
and
DIG2
fields change to display the
programmable DFS frequency with a “P” prefix.
FSYNC
is an 8kHz output that can be configured as a 50% duty cycle clock or a frame pulse and can optionally be
inverted.
MFSYNC
is a 2kHz output that can be similarly configured.
Table 4-5. Mapping Between Output Clock Software Fields and DS3106 Register Fields
SOFTWARE FIELD
DS3106 REGISTER FIELDS
DIG1
MCR6:DIG1SS, MCR7:DIG1F
DIG2
MCR6:DIG2SS, MCR7:DIG2F, MCR7:DIG2AF
OC3 and OC6
OCR2 and OCR3
FSYNC
OCR4:FSEN, FSCR1:8KPUL, FSCR1:8KINV
MFSYNC
OCR4:MFSEN, FSCR1:2KPUL, FSCR1:2KINV
4.7
DPLL Frequency Limits, Phase Detectors, DPLL Lock Criteria
The DPLL frequency limits specify the hard and soft limits of the T0 DPLL frequency range. When the selected
reference exceeds the soft limit, the
SOFTLIM
LED turns red but the selected reference is not disqualified. If the
FLLOL
(frequency limit loss of lock) box is checked in the
DPLL LOCK CRITERIA
box, when the selected
reference exceeds the hard limit the DPLL will lose lock (transition to LOL state).
The remaining fields are advanced topics. See
and the DS3106 data sheet for more details.
Table 4-6. Mapping Between DPLL Software Fields and DS3106 Register Fields
SOFTWARE FIELD
DS3106 REGISTER FIELDS
MCPDEN
PHLIM2:MCPDEN
USEMCPD
PHLIM2:USEMCPD
D180
TEST1:D180
COARSELIM
PHLIM2:COARSELIM
FINELIM
PHLIM1:FINELIM
FLEN
PHLIM1:FLEN
CLEN
PHLIM2:CLEN
FLLOL
DLIMIT3:FLLOL
NALOL
PHLIM1:NALOL
HARD LIMIT
HARDLIM[9:0] in DLIMIT1 and DLIMIT2
SOFT LIMIT
DLIMIT3:SOFTLIM
4.8
REFCLK Calibration
Any known frequency error in the local oscillator can be calibrated out inside the DS3106 by setting the ppm value
in the
REFCLK CAL
box. Also, the significant edge of the REFCLK signal can be selected in
XOEDGE
field.
Table 4-7. Mapping Between REFCLK Software Fields and DS3106 Register Fields
SOFTWARE FIELD
DS3106 REGISTER FIELDS
REFCLK slider/text box
MCLKFREQ[15:0] in MCLK1 and MCLK2
XOEDGE
MCR3:XOEDGE