Mercury 2 Reference Manual
v1.0 August 2, 2019
© 2019 MicroNova LLC
www.micro-nova.com
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DIRECT I/O
There are ten input/output pins that correct directly to the Artix-7 FPGA without any additional level-shifting
circuitry. Three of these inputs are global clock inputs: direct I/O 0 and 1 are single-region clock-capable (SRCC)
input pin, while direct I/O 9 is a multi-region clock-capable (MRCC) input pin. Three pairs of the direct I/O can be
used as XADC auxiliary inputs. Four pairs can be used as TMDS_33 differential I/O.
DIRECT IO
FPGA PIN
XADC AUX Input
Clock-Capable Input
TMDS pairs
0
C12
n/a
Single-region (SRCC)
Bank 15 L11P
1
C11
n/a
Single-region (SRCC)
Bank 15 L11N
2
D9
n/a
n/a
n/a
3
A9
XADC Aux[8] N
n/a
Bank 15 L2N
4
A8
XADC Aux[8] P
n/a
Bank 15 L2P
5
A10
XADC Aux[1] N
n/a
Bank 15 L3N
6
B9
XADC Aux[1] P
n/a
Bank 15 L3P
7
B6
XADC Aux[12] P
n/a
Bank 35 L2P
8
B5
XADC Aux[12] N
n/a
Bank 35 L2N
9
E12
n/a
Multi-region (MRCC)
n/a
ON-CHIP ANALOG-TO-DIGITAL CONVERTER: XILINX XADC
The Xilinx Artix-7 contains an internal dual-channel 12-bit analog-to-digital converter capable of operating at
1 MSPS. Either channel can be driven by a range of inputs, including the direct coax input, as well as aux inputs on
direct I/O pins 3-8. The XADC can also be used to monitor the FPGA internal temperature and power supply rails.
The
Mercury 2
board contains a precision external 1.25V reference (U15) that is connected to the V
REF
input of the
XADC. The XADC can also use an internal reference, this can be accomplished by removing the external reference
(U15) and adding a 0
Ω
resistor to R22. When using the external reference (U15), R22 should not be populated.
The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). Refer
to the MicroNova website sample code and tutorials dealing with the XADC component. Refer to the Xilinx XADC
User Guide (UG480) for more details on XADC usage.
EXTERNAL ANALOG-TO-DIGITAL CONVERTER: MCP3008
Mercury 2
is equipped with an onboard Microchip MCP3008 SPI ADC. It can
sample 8-channels with 10-bit resolution, at 200 KSPS sample rate. MCP3008
ADC is capable of sampling voltages in the range of 0V to 5V. This dynamic
range is modifiable using the external VREF pin. Communication with the
MCP3008 is achieved using SPI. A sample driver in VHDL can be found on the
MicroNova website.
ADC PIN
FPGA PIN
ADC SCK
P10
ADC MOSI
J16
ADC MISO
G15
ADC CSN
K15
