Microchip Technology USB5744, Руководство пользователя

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2015-2017 Microchip Technology Inc. DS00001855E-page 35
USB5744
9.6.3 RESET AND CONFIGURATION STRAP TIMING
Figure 9-4 illustrates the
RESET_N
pin timing requirements and its relation to the configuration strap pins. Assertion of
RESET_N
is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to Section
8.2, "Resets" for additional information on resets. Refer to Section 3.4, "Configuration Straps and Programmable Func-
tions" for additional information on configuration straps.
9.6.4 USB TIMING
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the
Uni-
versal Serial Bus Specification
. Please refer to the
Universal Serial Bus Revision 3.1 Specification
, available at http://
www.usb.org/developers/docs.
9.6.5 I
2
C TIMING
All device I
2
C signals conform to the 400KHz Fast Mode (Fm) voltage, power, and timing characteristics/specifications
as set forth in the
I
2
C-Bus Specification
. Please refer to the
I
2
C-Bus Specification
, available at http://www.nxp.com/doc-
uments/user_manual/UM10204.pdf.
9.6.6 SMBUS TIMING
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the
Sys-
tem Management Bus Specification.
Please refer to the
System Management Bus Specification
, Version 1.0, available
at http://smbus.org/specs.
FIGURE 9-4: RESET_N CONFIGURATION STRAP TIMING
TABLE 9-7: RESET_N CONFIGURATION STRAP TIMING
Symbol Description Min Typ Max Units
t
rstia
RESET_N
input assertion time 5

s
t
csh
Configuration strap pins hold after
RESET_N
deassertion 1 ms
Note:
The clock input must be stable prior to
RESET_N
deassertion.
Configuration strap latching and output drive timings shown assume that the Power-On reset has finished
first otherwise the timings in
Section 9.6.2, "Power-On and Configuration Strap Timing" apply.
RESET_N
Configuration
Straps
t
rstia
t
csh