2.
Overview
The MVIO pins, located on PORTC, are powered by a separate VDDIO2 pin while the rest are powered by VDD. This
allows for additional power domain at a different voltage level within the limits of the Electrical Characteristics of each
device.
Figure 2-1. 48-Pin VQFN/TQFP Pinout Diagram
1
2
3
4
4
4
4
3
4
2
4
1
4
0
3
9
3
8
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
2
4
2
3
3
7
36
35
34
12
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
45
46
47
48
G
N
D
V
D
D
PA5
PA6
PA7
P
D
2
P
D
3
PD6
PD7
PB0
P
D
0
P
D
1
P
A
2
P
A
3
PB1
PB2
PB3
PE1
PE2
PE0
PE3
PF0 (XTAL32K1)
PF1 (XTAL32K2)
P
A
1 (XT
ALHF
2)
P
A
0
(XT
ALHF1
)
PD5
P
A
4
PF2
PC0
PC1
P
C
4
P
C
5
P
C
3
PC2
P
C
6
P
C
7
P
F
3
P
F
4
U
P
D
I
P
F
5
P
F6
V
D
DIO2
PB4
PB5
G
N
D
GND
AVDD
P
D
4
Power
Power Supply
Ground
Pin on AVDD Power Domain
Functionality
Programming/Debug
Clock/Crystal
Analog Function
Digital Function Only
Pin on VDD Power Domain
Pin on VDDIO2 Power Domain
These pins are capable of the same digital behavior as regular I/O pins, for example GPIO, serial communication
(USART, SPI, I
2
C), or connected to PWM peripherals. The input Schmitt Trigger levels are scaled according to the
VDDIO2 voltage, as described in the Electrical Characteristics section of the data sheet.
A configuration fuse determines the MVIO supply mode. The loss or gain of power on VDDIO2 is signaled by a status
register bit. This status bit has corresponding interrupt and event functionality.
A divided-down VDDIO2 voltage is available as input to the ADC.
TB3287
Overview
©
2020 Microchip Technology Inc.
Technical Brief
DS90003287A-page 5
