3.2.2.2
Jumper Configurations
The following table describes the functionality of the jumpers.
Table 3-11. Jumper Configuration
Jumper
Label
Default Setting
Function
J1
ERASE
Open
PL485 Flash memory code erase
(closed = erase)
J13
DIS CDC
Open
Enable debug UART in JLINK
(closed = Disable UART in JLINK (J12 DBG USB))
J14
DIS JLINK
Open
Select between JLINK or JTAG programmer
(closed = Disable JLINK enable J15 JTAG programmer)
Note:
Pitch jumpers are 2.54 mm (0.1").
3.2.2.3
Test Points
Some test points (probes and pads) have been placed on the PL485-EK board for the verification of the main signals.
Table 3-12. Test Point Probes
Reference
Function
TP6
5V
TP8
GND
TP9
GND
TP10
3V3
TP16
PLC signal
Table 3-13. Test Point Pads
Reference
Function
Reference
Function
TP1
Pin PL NRST
TP13
PL-
TP2
Pin JTAGSEL
TP14
Pin PL TXRX0
TP3
VDC
TP15
Pin PL TXRX1
TP4
GND
TP17
PLC Signal
TP5
5V REG
TP18
Xplained PRO ID
TP7
GND
TP19
Pin PA31, LED0 D19
TP8
GND
TP20
Pin PA19, LED1 D20
TP9
GND
TP21
Pin PL VZC
TP11
3.3V
TP22
3.3V JLINK
TP12
PL+
-
-
3.3
Hardware Description – System
3.3.1
PL485
The PL485-EK board is equipped with a PL485 device in 121-Ball TFBGA (10x10, 0.8 mm ball pitch).
PL485-EK
PL485-EK Board
©
2020 Microchip Technology Inc.
User Guide
DS50002954B-page 12
