Introduction
Microsemi Proprietary and Confidential UG0862 User Guide Revision 1.0
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Introduction
Microsemi’s High-Definition Multimedia Interface (HDMI) transmitter IP supports transmitting video data
described in the HDMI standard specification.
HDMI TX IP features are:
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Supports HDMI 2.0 and HDMI 1.4
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Supports 1, 2, and 4 pixels per clock input
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Supports 8-bits color depth
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Supports up to 4K resolutions of 4096x2160 at 60 Hz
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Supports Encoding Scheme - TMDS
HDMI is a high-speed, serial, digital signaling system that is designed to transmit large amounts of digital
data over a long cable length. To achieve these goals, HDMI utilizes Transition Minimized Differential
Signaling (TMDS), which is optimized for robust digital data transmission.
A TMDS link consists of a single clock channel and three data channels. The video pixel clock is
transmitted on the TMDS clock channel, which helps to keep the signals in synchronization. Video data is
carried as 24-bit pixels on the three TMDS data channels, where each data channel is designated for
red, green, and blue color component.
TMDS encoder allows transmitting serial data at a high speed, while minimizing potential for EMI
(Electro-Magnetic Interference) over copper cables by minimizing the number of transitions (reducing
interference between channels), achieves DC balance, on the wires, by keeping the number of ones and
zeros, on the line nearly equal.
HDMI TX IP is designed to be used along with PolarFire device transceivers. The IP is compatible with
HDMI 1.4 and HDMI 2.0 and supports up to 60 frames per second with a maximum bandwidth of
18 Gbps. The IP uses TMDS encoder that converts the 8 bits per channel into the 10-bit DC-balanced,
transition minimized sequence, which is then transmitted serially at a rate of 10 bits per pixel per channel
on the video data period. During the video blanking period, control tokens are transmitted that are
generated based on hsync and vsync signals.
The control tokens can have one of the four predefined values:
10'b1101010100, 10'b0010101011, 10'b0101010100, and 10'b1010101011. Control data characters are
designed to have a large number (7) of transitions to help the receiver synchronize its clock with the
transmitter clock.
The HDMI TX IP can process the data at 1, 2, or 4 pixels per clock. When the IP operates in 2 or 4 pixels
per clock, it also produces the output in the form of two or four encoded pixels per clock.
Содержание Microsemi HDMI TX IP
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