Microchip Technology Microsemi HDMI TX IP, Руководство пользователя

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Hardware Implementation
Microsemi Proprietary and Confidential UG0862 User Guide Revision 1.0 3
3 Hardware Implementation
The following figure illustrates the HDMI TX IP in 1 pixel mode for PolarFire devices:
Figure 1 •
HDMI TX IP Block Diagram
In the TMDS encoder, the first stage is an XOR/XNOR operation, which minimizes the number of
transitions, and the second stage is an INV/NONINV, which minimizes the disparity (DC balance). The
extra two bits are added at this stage of operation. Control data (hsync and vsync) is encoded to 10 bits
in 4 possible combinations to help the receiver synchronize its clock with the transmitter clock. A
Transceiver should be used along with the HDMI TX IP to serialize the 10 bits (1 pixel mode) or 40 bits (4
pixels mode).
SYS_CLK_I
RESET_N_I
DATA_VALID_I
H_SYNC_I
V_SYNC_I
DATA_R_I [7:0]
DATA_G_I [7:0]
DATA_B_I [7:0]
10'h1F
TMDS_R_O [9:0]
TMDS_G_O [9:0]
TMDS_B_O [9:0]
TX_PLL
DISPLAY_CLK
LANE_TX_CLK_R
LANE_CLK_TXD[P,N]
LANE_R_TXD[P,N]
LANE_G_TXD[P,N]
LANE_B_TXD[P,N]
LANE_CLK_TX_DATA[9:0]
LANE_R_TX_DATA[9:0]
LANE_G_TX_DATA[9:0]
LANE_B_TX_DATA[9:0]
HDMI TX
XCVR
LANE_CLK_CDR_REF_CLK_FAB
LANE_R_CDR_REF_CLK_FAB
LANE_G_CDR_REF_CLK_FAB
LANE_B_CDR_REF_CLK_FAB