Microchip Technology Microsemi HDMI TX IP, Руководство пользователя

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Inputs and Outputs
Microsemi Proprietary and Confidential UG0862 User Guide Revision 1.0 8
4.4 Timing Diagrams
The following timing diagram for HDMI TX IP shows video data and control data periods for 1 pixel per
clock.
Figure 10 • HDMI TX IP Timing Diagram of Video Data for 1 Pixel Per Clock
The following diagram shows the 4 combinations of control data.
Figure 11 •
HDMI TX IP Timing Diagram of Control Data for 1 Pixel Per Clock
4.5 Resource Utilization
HDMI TX IP is implemented in PolarFire FPGA (MPF300T - 1FCG1152I Package). The following table
describes the resources utilized by the FPGA, when pixels per clock = 1.
The following table describes the resources utilized by the FPGA, when pixels per clock = 4.
Table 4 • Resource Utilization for 1 Pixel Per Clock
Resource Usage
DFFs 42
4LUTs 250
Table 5 • Resource Utilization for 4 Pixels Per Clock
Resource Usage
DFFs 168
4LUTs 1100