Board Details and Configuration
2018 Microchip Technology Inc.
DS50002726A-page 15
2.5.1
PHY Ports - Integrated Magnetic Jacks
PHY ports 1 and 2 (J2 and J6) support 10BASE-T/100BASE-TX/1000BASE-T with
both Auto-Negotiation and Auto MDI/MDI-X enabled as the power-up defaults.
2.5.2
PHY Ports - LEDs
Two Dual-LEDs (D2 and D6) provide the link status for PHY ports 1 and 2, respectively.
The LED descriptions are listed in
.
2.5.3
Pin Strapping Configuration
As the power-up or reset defaults, the KSZ9563 device is configured via internal or
external pull-up or pull-down resistors to the following settings:
• PHY Ports 1 and 2:
Auto-Negotiation enabled and Energy-Efficient Ethernet
(EEE) enabled
•
MAC Port 3:
RGMII Mode at 1000-Mbps speed
•
Start Switch:
The switch forwards packets immediately after hardware reset.
•
Management:
SPI Slave mode
The In-band Management Access (IBA) mode and Quiet-Wire
®
pin strappings can be
enabled or disabled using the 3-pin jumpers in
. Set the desired jumper set-
tings prior to board power-up, hardware reset, or both.
Refer to the board schematics in
and the KSZ9563 data
sheet for further details on the pin strappings.
2.5.4
GPIO Signal Headers
shows the GPIO signals that support the IEEE 1588 Precision Time Protocol
(PTP).
TABLE 2-1:
PHY PORTS - LED DESCRIPTION
LED
LED Color
Description
D2, D6
Green
Solid color: 1-Gbps Link
Blinking: Activity (RX, TX)
Red
Solid color: 100-Mbps Link
Blinking: Activity (RX, TX)
Orange
Solid color: 10-Mbps Link
Blinking: Activity (RX, TX)
Off
Link off
TABLE 2-2:
PIN STRAPPING JUMPERS
Jumper
Label
Description
Close pins
1-2
Close pins
2-3
J1
IBA mode
IBA provides full register read and
write access via any one of the three
data ports.
Disable
Enable
(default)
J5
Quiet-Wire
Quiet-Wire filtering is implemented
on-chip to enhance 100BASE-TX
EMC performance by reducing both
conducted and radiated emissions
from the TXP/M signal differential
pair.
Enable
Disable
(default)
