Installation and Operation
2021 Microchip Technology Inc.
DS50003160A-page 19
2.4
INTERFACE CONNECTIONS
TABLE 2-3:
J2 CONTROL INTERFACE SIGNALS
Pin No.
Name
Test Point
I/O Type
Signal Direction
J2-A2
SCK
—
LVCMOS-2.5V Input
EEPROM Serial Clock Input
J2-B2
CSB
—
LVCMOS-2.5V Input
EEPROM Chip Select Input
J2-A3
MISO
—
LVCMOS-2.5V Output EEPROM Serial Data Output
J2-B3
MOSI
—
LVCMOS-2.5V Input
EEPROM Serial Data input
J2-A5
CLR
TP15
LVCMOS-3.3V Input
HV2916 Latch Clear Logic Input
J2-B5
CLK
TP14
LVCMOS-3.3V Input
HV2916 Clock Logic Input
J2-C5
LE
TP12
LVCMOS-3.3V Input
HV2916 Latch Enable Logic Input
J2-A6
DIN
TP20
LVCMOS-3.3V Input
HV2916 Data In Logic Input
J2-C6
1_A
TP11
LVCMOS-3.3V Input
Ch1 Pulser input for NMOS to V
NN
J2-D6
1_B
TP10
LVCMOS-3.3V Input
Ch1 Pulser input for PMOS to V
PP
J2-A7
1_DMP
TP9
LVCMOS-3.3V Input
Ch1 Pulser Damp Input for PMOS/NMOS to GND
J2-B7
2_A
TP19
LVCMOS-3.3V Input
Ch2 Pulser input for NMOS to V
NN
J2-C7
2_B
TP18
LVCMOS-3.3V Input
Ch2 Pulser input for PMOS to V
PP
J2-D7
2_DMP
TP17
LVCMOS-3.3V Input
Ch2 Pulser Damp Input for PMOS/NMOS to GND
Содержание EV07D36A
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