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dsPIC33/PIC24 Family Reference Manual

DS30009711C-page 2



2006-2019 Microchip Technology Inc.

1.0

INTRODUCTION

The general purpose I/O pins can be considered the simplest of peripherals. They allow the PIC

®

MCU to monitor and control other devices. To add flexibility and functionality to a device, some
pins are multiplexed with alternate function(s). These functions depend on which peripheral
features are on the device. In general, when a peripheral is functioning, that pin may not be used
as a general purpose I/O pin.
Most of the dsPIC33/PIC24 devices support the Peripheral Pin Select (PPS) feature. The PPS
constitutes pins which users can map to the input and/or output of some digital peripherals.

shows a block diagram of a typical I/O port. This block diagram does not take into

account peripheral functions that may be multiplexed onto the I/O pin.

Figure 1-1:

Dedicated Port Structure Block Diagram

Note:

This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33/PIC24 devices.
Please consult the note at the beginning of the

“I/O Ports”

chapter in the current

device data sheet to check whether this document supports the device you are
using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Website at:

http://www.microchip.com

WR LATx

TRISx Latch

I/O Pin

WR PORTx

Data Bus

Data Latch

Read LATx

Read PORTx

Read TRISx

WR TRISx

I/O Cell

Dedicated Port Module

0

1

Open-Drain Selection

Q

D

CK

Q

D

CK Q

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Содержание dsPIC24 series

Страница 1: ...following topics 1 0 Introduction 2 2 0 I O Port Control Registers 3 3 0 Peripheral Multiplexing 7 4 0 Peripheral Pin Select 9 5 0 Port Descriptions 19 6 0 Change Notification CN Pins 19 7 0 Register...

Страница 2: ...als Figure 1 1 shows a block diagram of a typical I O port This block diagram does not take into account peripheral functions that may be multiplexed onto the I O pin Figure 1 1 Dedicated Port Structu...

Страница 3: ...ify Write RMW operations There fore a write to a port implies that the port pins are read the value is modified and then written back to the port data latch Care should be taken when Read Modify Write...

Страница 4: ...is 0 then the pin is configured for a normal digital output ODC bit is valid only for output pins After a Reset the status of all the bits of the ODCx register is set to 0 The open drain feature allo...

Страница 5: ...t is cleared x Bit is unknown bit 15 0 TRISx 15 0 PORTx Data Direction Control bits 1 1 The pin is an input 0 The pin is an output Note 1 Refer to the specific device data sheet for the actual impleme...

Страница 6: ...bit 15 0 LATx 15 0 PORTx Data Latch bits 1 1 The latch content is 1 0 The latch content is 0 Note 1 Refer to the specific device data sheet for the actual implementation R W 0 R W 0 R W 0 R W 0 R W 0...

Страница 7: ...e peripheral functions may be multiplexed on each I O pin The priority of the peripheral function depends on the order of the pin description in the pin diagram of the specific product data sheet Figu...

Страница 8: ...Software Input Pin Control Some of the functions assigned to an I O pin may be input functions that do not take control of the pin output driver An example of one such peripheral is the input capture...

Страница 9: ...ates a remappable peripheral and n is the remappable pin number If the pin supports only the input function Peripheral Pin Select feature then it will be designated as RPIn For more details refer to t...

Страница 10: ...ch Read PORTx Read TRISx n 0 WR TRISx Peripheral 2 Output Enable I O Peripheral n Output Enable PIO Module Output Multiplexers Output Function Read LATx 0 1 Peripheral Input Q Peripheral 1 Output Enab...

Страница 11: ...ociated with a peripheral dictates the pin it will be mapped to The RPINRx reg isters refer to Register 4 3 and Table 4 1 contain sets of 6 bit fields with each set associated with one of the remappab...

Страница 12: ...pture 2 IC2 RPINR7 13 8 IC2R 5 0 Input Capture 3 IC3 RPINR8 5 0 IC3R 5 0 Input Capture 4 IC4 RPINR8 13 8 IC4R 5 0 Input Capture 5 IC5 RPINR9 5 0 IC5R 5 0 Output Compare Fault A OCFA RPINR11 5 0 OCFAR...

Страница 13: ...is mapped to the pin see Table 4 1 and Figure 4 3 The peripheral outputs that support Peripheral Pin Selection have no default pins Since the RPORy registers reset to all 0 s the outputs are all disc...

Страница 14: ...on 1 RPnR 5 0 Output Name NULL 0 The pin is an I O Port pin C1OUT 1 RPn tied to Comparator 1 Output C2OUT 2 RPn tied to Comparator 2 Output U1TX 3 RPn tied to UART1 Transmit U1RTS 4 RPn tied to UART1...

Страница 15: ...e the unlock sequence should be performed by writing inline assembly or using built in functions provided by the MPLAB C30 C Compiler IOLOCK remains in one state until changed This allows all of the P...

Страница 16: ...ral output to a particular pin does not automatically perform any other configuration of the pin s I O circuitry This means adding a pin selectable output to a pin may mean inadvertently driving an ex...

Страница 17: ...p w3 n pop w2 n pop w1 Configure Input Functions Assign U1Rx To Pin RP0 RPINR18bits U1RXR 0 0 represents RP0 Assign U1CTS To Pin RP1 RPINR18bits U1CTSR 1 1 represents RP1 Configure Output Functions As...

Страница 18: ...in bits 1 bit 7 6 Unimplemented Read as 0 bit 5 0 Input Function Bits 5 0 Assign Peripheral to Corresponding RPn Pin bits 1 Note 1 Here n represents the peripheral select input pin number 2 Here x rep...

Страница 19: ...registers associated with the CN module The CNENx registers contain the CNxIE control bits where x denotes the number of the CN input pin The CNxIE bit must be set for a CN input pin to interrupt the...

Страница 20: ...condition and set up the CN logic to detect the next pin change The current PORTx value can be compared to the PORT read value obtained at the last CN interrupt to determine the pin that changed The C...

Страница 21: ...x3 Rx2 Rx1 Rx0 xxxx ODCx PORTx Open Drain Control bits 0000 Note 1 Refer to the specific device data sheet for the I O Ports register map details Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 B...

Страница 22: ...pecifically for the dsPIC33 PIC24 families of devices but the concepts are pertinent and could be used with modification and possible limitations The current application notes related to the I O Ports...

Страница 23: ...evision A August 2006 This is the initial released revision of this document Revision B May 2007 Added PPS section removed JTAG boundary scan section and added PPS SFR table Revision C March 2019 Upda...

Страница 24: ...dsPIC33 PIC24 Family Reference Manual DS30009711C page 24 2006 2019 Microchip Technology Inc NOTES...

Страница 25: ...TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology...

Страница 26: ...5300 China Xian Tel 86 29 8833 7252 China Xiamen Tel 86 592 2388138 China Zhuhai Tel 86 756 3210040 ASIA PACIFIC India Bangalore Tel 91 80 3090 4444 India New Delhi Tel 91 11 4160 8631 India Pune Tel...

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